Shi; Leathen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shi; Leathen.The latest application filed is for "semiconductor device including built-in crack-arresting film structure".

Company Profile

3.56.58

Shi; Leathen - Yorktown Heights NY
Shi, Leathen - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Wafer level integration including design/co-design, structure process, equipment stress management, and thermal management Grant 10,811,305 - Hung , et al. October 20, 2	2020-10-20
Semiconductor device including built-in crack-arresting film structure Grant 10,615,139 - Lin , et al.	2020-04-07
Semiconductor device including built-in crack-arresting film structure Grant 10,211,178 - Lin , et al. Feb	2019-02-19
Semiconductor Device Including Built-in Crack-arresting Film Structure App 20180226374 - Lin; Wei ; et al.	2018-08-09
Semiconductor device including built-in crack-arresting film structure Grant 10,020,279 - Lin , et al. July 10, 2	2018-07-10
Wafer Level Integration Including Design/co-design, Structure Process, Equipment Stress Management, And Thermal Management App 20180082888 - HUNG; Li-Wen ; et al.	2018-03-22
Epitaxial lift-off process with guided etching Grant 9,865,469 - Cheng , et al. January 9, 2	2018-01-09
Semiconductor Device Including Built-in Crack-arresting Film Structure App 20170221850 - Lin; Wei ; et al.	2017-08-03
Epitaxial Lift-off Process With Guided Etching App 20170154783 - Cheng; Cheng-Wei ; et al.	2017-06-01
Epitaxial lift-off process with guided etching Grant 9,653,308 - Cheng , et al. May 16, 2	2017-05-16
Epitaxial Lift-off Process With Guided Etching App 20170062232 - Cheng; Cheng-Wei ; et al.	2017-03-02
Semiconductor device including built-in crack-arresting film structure Grant 9,536,853 - Lin , et al. January 3, 2	2017-01-03
Semiconductor Device Including Built-in Crack-arresting Film Structure App 20160322324 - Lin; Wei ; et al.	2016-11-03
Flattened substrate surface for substrate bonding Grant 9,355,936 - Cooney, III , et al. May 31, 2	2016-05-31
Semiconductor Device Including Built-in Crack-arresting Film Structure App 20160141263 - Lin; Wei ; et al.	2016-05-19
Accurate control of distance between suspended semiconductor nanowires and substrate surface Grant 8,927,405 - Cohen , et al. January 6, 2	2015-01-06
Accurate control of distance between suspended semiconductor nanowires and substrate surface Grant 8,927,968 - Cohen , et al. January 6, 2	2015-01-06
Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation Grant 8,877,606 - Dennard , et al. November 4, 2	2014-11-04
Flattened Substrate Surface For Substrate Bonding App 20140209908 - Cooney, III; Edward C. ; et al.	2014-07-31
Flattened substrate surface for substrate bonding Grant 8,778,737 - Cooney, III , et al. July 15, 2	2014-07-15
Accurate Control Of Distance Between Suspended Semiconductor Nanowires And Substrate Surface App 20140166982 - Cohen; Guy ; et al.	2014-06-19
Accurate Control Of Distance Between Suspended Semiconductor Nanowires And Substrate Surface App 20140166983 - Cohen; Guy ; et al.	2014-06-19
High-k dielectric and silicon nitride box region Grant 8,637,381 - Leobandung , et al. January 28, 2	2014-01-28
Method of forming isolation structures for SOI devices with ultrathin SOI and ultrathin box Grant 8,586,426 - Dennard , et al. November 19, 2	2013-11-19
Soi Structures Including A Buried Boron Nitride Dielectric App 20130196483 - Dennard; Robert H. ; et al.	2013-08-01
Soi Structures Including A Buried Boron Nitride Dielectric App 20130193445 - Dennard; Robert H. ; et al.	2013-08-01
Isolation structures for SOI devices with ultrathin SOI and ultrathin box Grant 8,492,838 - Dennard , et al. July 23, 2	2013-07-23
Flattened Substrate Surface For Substrate Bonding App 20130105981 - Cooney, III; Edward C. ; et al.	2013-05-02
High-k Dielectric And Silicon Nitride Box Region App 20130093039 - LEOBANDUNG; EFFENDI ; et al.	2013-04-18
Adaptive chuck for planar bonding between substrates Grant 8,408,262 - Guo , et al. April 2, 2	2013-04-02
Adaptive Chuck For Planar Bonding Between Substrates App 20120312452 - Guo; Dechao ; et al.	2012-12-13
Isolation Structures For Soi Devices With Ultrathin Soi And Ultrathin Box App 20120302039 - Dennard; Robert H. ; et al.	2012-11-29
Low Cost Fabrication Of Double Box Back Gate Silicon-on-insulator Wafers With Subsequent Self Aligned Shallow Trench Isolation App 20120112309 - Dennard; Robert H. ; et al.	2012-05-10
Back-gated fully depleted SOI transistor Grant 8,030,145 - Chang , et al. October 4, 2	2011-10-04
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) Grant 8,017,499 - Chan , et al. September 13, 2	2011-09-13
Back-gated Fully Depleted Soi Transistor App 20110171792 - Chang; Leland ; et al.	2011-07-14
Isolation Structures For Soi Devices With Ultrathin Soi And Ultrathin Box App 20110115021 - Dennard; Robert H. ; et al.	2011-05-19
Adaptive Chuck For Planar Bonding Between Substrates App 20110083786 - Guo; Dechao ; et al.	2011-04-14
Preparation of high quality strained-semiconductor directly-on-insulator substrates Grant 7,897,480 - Chu , et al. March 1, 2	2011-03-01
Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer Grant 7,767,546 - Dennard , et al. August 3, 2	2010-08-03
Low Cost Fabrication Of Double Box Back Gate Silicon-on-insulator Wafers With Built-in Shallow Trench Isolation In Back Gate Layer App 20100187607 - Dennard; Robert H. ; et al.	2010-07-29
Low Cost Fabrication Of Double Box Back Gate Silicon-on-insulator Wafers With Subsequent Self Aligned Shallow Trench Isolation App 20100176482 - Dennard; Robert H. ; et al.	2010-07-15
Low Cost Fabrication Of Double Box Back Gate Silicon-on-insulator Wafers With Built-in Shallow Trench Isolation In Back Gate Layer App 20100176453 - Dennard; Robert H. ; et al.	2010-07-15
Low Cost Fabrication Of Double Box Back Gate Silicon-on-insulator Wafers App 20100176495 - Chu; Jack O. ; et al.	2010-07-15
Low temperature fusion bonding with high surface energy using a wet chemical treatment Grant 7,713,837 - Chan , et al. May 11, 2	2010-05-11
Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques Grant 7,704,815 - Chu , et al. April 27, 2	2010-04-27
Strained silicon CMOS on hybrid crystal orientations Grant 7,691,688 - Chan , et al. April 6, 2	2010-04-06
Low temperature fusion bonding with high surface energy using a wet chemical treatment Grant 7,566,631 - Chan , et al. July 28, 2	2009-07-28
Low-cost strained SOI substrate for high-performance CMOS technology Grant 7,528,056 - Ieong , et al. May 5, 2	2009-05-05
Multiple layer and crystal plane orientation semiconductor substrate Grant 7,521,735 - Furukawa , et al. April 21, 2	2009-04-21
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) Grant 7,507,989 - Chan , et al. March 24, 2	2009-03-24
Method for preparing 2-dimensional semiconductor devices for integration in a third dimension Grant 7,488,630 - Frank , et al. February 10, 2	2009-02-10
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) Grant 7,485,518 - Chan , et al. February 3, 2	2009-02-03
METHOD OF CREATING DEFECT FREE HIGH Ge CONTENT (> 25%) SiGe-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES App 20090004831 - Chu; Jack O. ; et al.	2009-01-01
Method of creating defect free high Ge content (> 25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques Grant 7,445,977 - Chu , et al. November 4, 2	2008-11-04
Preparation Of High Quality Strained-semiconductor Directly-on-insulator Substrates App 20080261055 - Chu; Jack O. ; et al.	2008-10-23
Strained Silicon Cmos On Hybrid Crystal Orientations App 20080254594 - Chan; Kevin K. ; et al.	2008-10-16
Low Temperature Fusion Bonding With High Surface Energy Using A Wet Chemical Treatment App 20080227270 - Chan; Kevin K. ; et al.	2008-09-18
STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI) App 20080220588 - Chan; Kevin K. ; et al.	2008-09-11
Method For Preparing 2-dimensional Semiconductor Devices For Integration In A Third Dimension App 20080217782 - Frank; David J. ; et al.	2008-09-11
Strained silicon CMOS on hybrid crystal orientations Grant 7,402,466 - Chan , et al. July 22, 2	2008-07-22
Low-cost Strained Soi Substrate For High-performance Cmos Technology App 20080171423 - Ieong; Meikei ; et al.	2008-07-17
Multiple Layer And Cyrstal Plane Orientation Semiconductor Substrate App 20080099844 - Furukawa; Toshiharu ; et al.	2008-05-01
Multiple Layer And Crystal Plane Orientation Semiconductor Substrate App 20080102566 - Furukawa; Toshiharu ; et al.	2008-05-01
STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI) App 20080042166 - Chan; Kevin K. ; et al.	2008-02-21
METHOD OF CREATING DEFECT FREE HIGH Ge CONTENT (> 25%) SiGe-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES App 20070218647 - Chu; Jack O. ; et al.	2007-09-20
STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI) App 20070155130 - Chan; Kevin K. ; et al.	2007-07-05
Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques Grant 7,235,812 - Chu , et al. June 26, 2	2007-06-26
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) Grant 7,217,949 - Chan , et al. May 15, 2	2007-05-15
SOI wafers with 30-100 .ANG. buried oxide (BOX) created by wafer bonding using 30-100 .ANG. thin oxide as bonding layer Grant 7,166,521 - Boyd , et al. January 23, 2	2007-01-23
Strained silicon CMOS on hybrid crystal orientations App 20060275961 - Chan; Kevin K. ; et al.	2006-12-07
Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processes Grant 7,138,683 - Guarini , et al. November 21, 2	2006-11-21
Low temperature fusion bonding with high surface energy using a wet chemical treatment App 20060194414 - Chan; Kevin K. ; et al.	2006-08-31
Multiple Layer And Crystal Plane Orientation Semiconductor Substrate App 20060186416 - Furukawa; Toshiharu ; et al.	2006-08-24
Strained silicon CMOS on hybrid crystal orientations Grant 7,087,965 - Chan , et al. August 8, 2	2006-08-08
Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques App 20060054891 - Chu; Jack O. ; et al.	2006-03-16
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) App 20060001088 - Chan; Kevin K. ; et al.	2006-01-05
Strained silicon CMOS on hybrid crystal orientations App 20050236687 - Chan, Kevin K. ; et al.	2005-10-27
Method of fabricating silicon devices on sapphire with wafer bonding at low temperature Grant 6,911,375 - Guarini , et al. June 28, 2	2005-06-28
Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processes App 20050070077 - Guarini, Kathryn W. ; et al.	2005-03-31
SOI wafers with 30-100 A buried oxide (BOX) created by wafer bonding using 30-100 A thin oxide as bonding layer App 20050042841 - Boyd, Diane C. ; et al.	2005-02-24
Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process Grant 6,841,831 - Hanafi , et al. January 11, 2	2005-01-11
SOI wafers with 30-100 .ANG. buried oxide (BOX) created by wafer bonding using 30-100 .ANG. thin oxide as bonding layer Grant 6,835,633 - Boyd , et al. December 28, 2	2004-12-28
Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes Grant 6,830,962 - Guarini , et al. December 14, 2	2004-12-14
Method of fabricating silicon devices on sapphire with wafer bonding at low temperature App 20040241958 - Guarini, Kathryn W. ; et al.	2004-12-02
Low temperature fusion bonding with high surface energy using a wet chemical treatment App 20040126993 - Chan, Kevin K. ; et al.	2004-07-01
Damascene double-gate MOSFET structure and its fabrication method Grant 6,686,630 - Hanafi , et al. February 3, 2	2004-02-03
SOI wafers with 30-100 A buried oxide (box) created by wafer bonding using 30-100 A thin oxide as bonding layer App 20040018699 - Boyd, Diane C. ; et al.	2004-01-29
Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region Grant 6,660,598 - Hanafi , et al. December 9, 2	2003-12-09
Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process App 20030211681 - Hanafi, Hussein I. ; et al.	2003-11-13
Method Of Forming A Fully-depleted Soi (silicon-on-insulator) Mosfet Having A Thinned Channel Region App 20030162358 - Hanafi, Hussein I. ; et al.	2003-08-28
Structural design and processes to control probe position accuracy in a wafer test probe assembly App 20030048108 - Beaman, Brian Samuel ; et al.	2003-03-13
Silicon on sapphire structure (devices) with buffer layer App 20020167068 - Hsu, Louis L. ; et al.	2002-11-14
Method of fabricating silicon devices on sapphire with wafer bonding App 20020168837 - Hsu, Louis L. ; et al.	2002-11-14
Damascene double-gate mosfet structure and its fabrication method App 20020105039 - Hanafi, Hussein Ibrahim ; et al.	2002-08-08
Encapsulated MEMS band-pass filter for integrated circuits and method of fabrication thereof Grant 6,399,406 - Chan , et al. June 4, 2	2002-06-04
Encapsulated MEMS band-pass filter for integrated circuits and method of fabrication thereof App 20010055864 - Chan, Kevin K. ; et al.	2001-12-27
Encapsulated MEMS brand-pass filter for integrated circuits Grant 6,262,464 - Chan , et al. July 17, 2	2001-07-17
Flip-Chip interconnections using lead-free solders Grant 6,224,690 - Andricacos , et al. May 1, 2	2001-05-01
Mechanical packaging and thermal management of flat mirror arrays Grant 5,764,314 - Narayan , et al. June 9, 1	1998-06-09
Method of forming a three dimensional high performance interconnection package Grant 5,531,022 - Beaman , et al. July 2, 1	1996-07-02
Non-destructive flex testing method and means Grant 5,424,634 - Goldfarb , et al. June 13, 1	1995-06-13
Three dimensional high performance interconnection package Grant 5,371,654 - Beaman , et al. December 6, 1	1994-12-06
Solder/polymer composite paste and method Grant 5,062,896 - Huang , et al. November 5, 1	1991-11-05