Sheu; Yi-Ming

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sheu; Yi-Ming.The latest application filed is for "structure and method for integrated circuit".

Company Profile

8.53.52

Sheu; Yi-Ming - Hsinchu TW
Sheu; Yi-Ming - Hsin-Chu N/A TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multi-gate device Grant 11,393,926 - Wei , et al. July 19, 2	2022-07-19
Horizontal gate all-around device having wrapped-around source and drain Grant 11,239,341 - Lin , et al. February 1, 2	2022-02-01
Multi-gate device Grant 11,145,762 - Wei , et al. October 12, 2	2021-10-12
Structure and Method for Integrated Circuit App 20210305426 - Kuang; Shin-Jiun ; et al.	2021-09-30
Semiconductor Device And Manufacturing Method Thereof App 20210242329 - KUANG; SHIN-JIUN ; et al.	2021-08-05
Semiconductor device and manufacturing method thereof Grant 11,004,955 - Kuang , et al. May 11, 2	2021-05-11
Method for manufacturing semiconductor structure Grant 10,868,175 - Kuang , et al. December 15, 2	2020-12-15
Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage Grant 10,861,972 - Wu , et al. December 8, 2	2020-12-08
Horizontal Gate All-Around Device Having Wrapped-Around Source and Drain App 20200365712 - Lin; Chun-Hsiung ; et al.	2020-11-19
Structure and Method for Integrated Circuit App 20200365735 - Kuang; Shin-Jiun ; et al.	2020-11-19
Structure and method for integrated circuit Grant 10,741,688 - Kuang , et al. A	2020-08-11
Horizontal gate all-around device having wrapped-around source and drain Grant 10,734,500 - Lin , et al.	2020-08-04
Semiconductor Device And Manufacturing Method Thereof App 20200144395 - KUANG; SHIN-JIUN ; et al.	2020-05-07
Multi-gate Device App 20200098923 - WEI; Huan-Sheng ; et al.	2020-03-26
Semiconductor device and manufacturing method thereof Grant 10,522,657 - Kuang , et al. Dec	2019-12-31
Structure and formation method of semiconductor device structure Grant 10,516,047 - Sio , et al. Dec	2019-12-24
Channel Strain Inducing Architecture And Doping Technique At Replacement Poly Gate (rpg) Stage App 20190245089 - Wu; Zhiqiang ; et al.	2019-08-08
Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage Grant 10,276,717 - Wu , et al.	2019-04-30
Horizontal Gate All-Around Device Having Wrapped-Around Source and Drain App 20190051734 - Lin; Chun-Hsiung ; et al.	2019-02-14
Semiconductor Device And Manufacturing Method Thereof App 20190019881 - KUANG; SHIN-JIUN ; et al.	2019-01-17
Horizontal gate-all-around device having wrapped-around source and drain Grant 10,109,721 - Lin , et al. October 23, 2	2018-10-23
Multi-gate Device App 20180301560 - WEI; Huan-Sheng ; et al.	2018-10-18
Semiconductor device and manufacturing method thereof Grant 10,084,063 - Kuang , et al. September 25, 2	2018-09-25
Multi-gate device and method of fabrication thereof Grant 10,008,603 - Wei , et al. June 26, 2	2018-06-26
Method For Manufacturing Semiconductor Structure App 20180166572 - KUANG; SHIN-JIUN ; et al.	2018-06-14
Structure And Formation Method Of Semiconductor Device Structure App 20180151729 - SIO; Kam-Tou ; et al.	2018-05-31
Multi-gate Device And Method Of Fabrication Thereof App 20180145176 - WEI; Huan-Sheng ; et al.	2018-05-24
Structure and Method for Integrated Circuit App 20180061986 - Kuang; Shin-Jiun ; et al.	2018-03-01
Epitaxial channel with a counter-halo implant to improve analog gain Grant 9,899,475 - Yu , et al. February 20, 2	2018-02-20
Dislocation stress memorization technique (DSMT) on epitaxial channel devices Grant 9,899,517 - Yu , et al. February 20, 2	2018-02-20
Semiconductor structure and manufacturing method thereof Grant 9,893,183 - Kuang , et al. February 13, 2	2018-02-13
Horizontal Gate-All-Around Device Having Wrapped-Around Source and Drain App 20170358500 - Lin; Chun-Hsiung ; et al.	2017-12-14
Semiconductor structure and manufacturing method thereof Grant 9,837,533 - Kuang , et al. December 5, 2	2017-12-05
Structure and method for integrated circuit Grant 9,831,341 - Kuang , et al. November 28, 2	2017-11-28
Horizontal gate-all-around device having wrapped-around source and drain Grant 9,754,840 - Lin , et al. September 5, 2	2017-09-05
Horizontal Gate-All-Around Device Having Wrapped-Around Source and Drain App 20170140996 - Lin; Chun-Hsiung ; et al.	2017-05-18
Dislocation Stress Memorization Technique (dsmt) On Epitaxial Channel Devices App 20170054022 - Yu; Tsung-Hsing ; et al.	2017-02-23
Channel Strain Inducing Architecture and Doping Technique at Replacement Poly Gate (RPG) Stage App 20160365447 - Wu; Zhiqiang ; et al.	2016-12-15
Multi-gate semiconductor devices Grant 9,502,409 - Ho , et al. November 22, 2	2016-11-22
Method of manufacturing an integrated circuit Grant 9,502,253 - Wu , et al. November 22, 2	2016-11-22
Dislocation stress memorization technique (DSMT) on epitaxial channel devices Grant 9,502,559 - Yu , et al. November 22, 2	2016-11-22
Epitaxial Channel With A Counter-halo Implant To Improve Analog Gain App 20160284800 - Yu; Tsung-Hsing ; et al.	2016-09-29
Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage Grant 9,455,346 - Wu , et al. September 27, 2	2016-09-27
Epitaxial channel with a counter-halo implant to improve analog gain Grant 9,425,099 - Yu , et al. August 23, 2	2016-08-23
Dislocation stress memorization technique (DSMT) on epitaxial channel devices Grant 9,419,136 - Yu , et al. August 16, 2	2016-08-16
Method for mechanical stress enhancement in semiconductor devices Grant 9,349,655 - Diaz , et al. May 24, 2	2016-05-24
Metal gate structure and manufacturing method thereof Grant 9,281,372 - Kuang , et al. March 8, 2	2016-03-08
Dislocation Stress Memorization Technique (dsmt) On Epitaxial Channel Devices App 20160035892 - Yu; Tsung-Hsing ; et al.	2016-02-04
Counter pocket implant to improve analog gain Grant 9,252,236 - Huang , et al. February 2, 2	2016-02-02
Metal Gate Structure And Manufacturing Method Thereof App 20160020297 - KUANG; SHIN-JIUN ; et al.	2016-01-21
Semiconductor Structure And Manufacturing Method Thereof App 20160013316 - KUANG; SHIN-JIUN ; et al.	2016-01-14
Semiconductor Structure And Manufacturing Method Thereof App 20160005863 - KUANG; SHIN-JIUN ; et al.	2016-01-07
Semiconductor Device And Manufacturing Method Thereof App 20150372142 - KUANG; Shin-Jiun ; et al.	2015-12-24
Structure and Method for Integrated Circuit App 20150364601 - Kuang; Shin-Jiun ; et al.	2015-12-17
Dislocation Stress Memorization Technique (DSMT) on Epitaxial Channel Devices App 20150295085 - Yu; Tsung-Hsing ; et al.	2015-10-15
Counter Pocket Implant To Improve Analog Gain App 20150243759 - Huang; Shih-Syuan ; et al.	2015-08-27
Epitaxial Channel With A Counter-halo Implant To Improve Analog Gain App 20150200139 - Yu; Tsung-Hsing ; et al.	2015-07-16
Multi-gate Semiconductor Devices App 20150162334 - HO; Jon-Hsu ; et al.	2015-06-11
Channel Strain Inducing Architecture And Doping Technique At Replacement Poly Gate (rpg) Stage App 20150162445 - Wu; Zhiqiang ; et al.	2015-06-11
Multi-gate semiconductor devices Grant 8,987,824 - Ho , et al. March 24, 2	2015-03-24
Multi-gate semiconductor devices and methods of forming the same Grant 8,981,479 - Wang , et al. March 17, 2	2015-03-17
Method Of Manufacturing An Integrated Circuit App 20150044847 - WU; Zhiqiang ; et al.	2015-02-12
Integrated circuits and manufacturing methods thereof Grant 8,859,380 - Wu , et al. October 14, 2	2014-10-14
Multi-gate Semiconductor Devices And Methods Of Forming The Same App 20140103438 - WANG; Chih-Ching ; et al.	2014-04-17
Multi-gate semiconductor devices and methods of forming the same Grant 8,623,716 - Wang , et al. January 7, 2	2014-01-07
Tunnel field-effect transistor with metal source Grant 8,587,075 - Bhuwalka , et al. November 19, 2	2013-11-19
Multi-gate Semiconductor Devices App 20130126981 - HO; Jon-Hsu ; et al.	2013-05-23
Multi-gate Semiconductor Devices And Methods Of Forming The Same App 20130113042 - Wang; Chih-Ching ; et al.	2013-05-09
Semiconductor device including an arrangement for suppressing short channel effects Grant 8,354,718 - Wang , et al. January 15, 2	2013-01-15
Integrated Circuits And Manufacturing Methods Thereof App 20120119298 - WU; Zhiqiang ; et al.	2012-05-17
Tunnel Field-Effect Transistor with Metal Source App 20100123203 - Bhuwalka; Krishna Kumar ; et al.	2010-05-20
New Method For Mechanical Stress Enhancement In Semiconductor Devices App 20100052065 - Diaz; Carlos H. ; et al.	2010-03-04
Method for reducing layout-dependent variations in semiconductor devices Grant 7,598,130 - Yang , et al. October 6, 2	2009-10-06
Semiconductor device having high drive current and method of manufacture therefor Grant 7,545,001 - Cheng , et al. June 9, 2	2009-06-09
Suppressing Short Channel Effects App 20080290412 - Wang; Chih-Chiang ; et al.	2008-11-27
Semiconductor Device With Raised Spacers App 20080290380 - Sheu; Yi-Ming ; et al.	2008-11-27
Recessed channel field effect transistor (FET) device Grant 7,429,769 - Diaz , et al. September 30, 2	2008-09-30
Narrow width effect improvement with photoresist plug process and STI corner ion implantation Grant 7,399,679 - Sheu , et al. July 15, 2	2008-07-15
N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications Grant 7,371,629 - Fu , et al. May 13, 2	2008-05-13
Method for reducing layout-dependent variations in semiconductor devices App 20080081382 - Yang; Chung-Heng ; et al.	2008-04-03
Narrow width effect improvement with photoresist plug process and STI corner ion implantation Grant 7,071,515 - Sheu , et al. July 4, 2	2006-07-04
Narrow width effect improvement with photoresist plug process and STI corner ion implantation App 20060079068 - Sheu; Yi-Ming ; et al.	2006-04-13
Recessed gate structure with reduced current leakage and overlap capacitance Grant 7,012,014 - Lin , et al. March 14, 2	2006-03-14
Method for fabricating a recessed channel field effect transistor (FET) device App 20060033158 - Diaz; Carlos H. ; et al.	2006-02-16
Method for fabricating a recessed channel field effect transistor (FET) device Grant 6,974,730 - Diaz , et al. December 13, 2	2005-12-13
Method for fabricating a recessed channel filed effect transistor (FET) device App 20050133830 - Diaz, Carlos H. ; et al.	2005-06-23
Recessed gate structure with reduced current leakage and overlap capacitance App 20050127433 - Lin, Da-Wen ; et al.	2005-06-16
Semiconductor device having high drive current and method of manufacture therefor App 20050110082 - Cheng, Shui-Ming ; et al.	2005-05-26
Self-aligned MOSFET having an oxide region below the channel App 20050012087 - Sheu, Yi-Ming ; et al.	2005-01-20
Narrow width effect improvement with photoresist plug process and STI corner ion implantation App 20050012173 - Sheu, Yi-Ming ; et al.	2005-01-20
Electrostatic discharge device protection structure Grant 6,800,516 - Chan , et al. October 5, 2	2004-10-05
Electrostatic discharge device protection structure App 20040140505 - Chan, Yi-Lang ; et al.	2004-07-22
N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications App 20040110392 - Fu, Chu-Yun ; et al.	2004-06-10
Method of forming a self-aligned twin well structure with a single mask Grant 6,703,187 - Sheu , et al. March 9, 2	2004-03-09
Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions Grant 6,673,683 - Sheu , et al. January 6, 2	2004-01-06
Planarizing method for fabricating gate electrodes Grant 6,670,226 - Lin , et al. December 30, 2	2003-12-30
Method of forming a self-aligned twin well structrue with a single mask App 20030129540 - Sheu, Yi-Ming ; et al.	2003-07-10

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.