Shetty; Shivananda S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shetty; Shivananda S..The latest application filed is for "processing tester information by trellising in integrated circuit technology development".

Company Profile

0.13.1

Shetty; Shivananda S. - Sunnyvale CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for storing and retrieving semiconductor tester information Grant 8,725,748 - Sundararajan , et al. May 13, 2	2014-05-13
Efficient storage of fail data to aid in fault isolation Grant 7,634,127 - Sundararajan , et al. December 15, 2	2009-12-15
Method and apparatus for correlating semiconductor process data with known prior process data Grant 7,263,451 - Erhardt , et al. August 28, 2	2007-08-28
Method and apparatus for using clustering method to analyze semiconductor devices Grant 7,197,435 - Erhardt , et al. March 27, 2	2007-03-27
Digital signal processing for real time classification of failure bitmaps in integrated circuit technology development Grant 7,155,652 - Shetty December 26, 2	2006-12-26
Wafer level global bitmap characterization in integrated circuit technology development Grant 7,137,085 - Wang , et al. November 14, 2	2006-11-14
Characterizing distribution signatures in integrated circuit technology Grant 7,099,789 - Wu , et al. August 29, 2	2006-08-29
System and method for processing tester information and visualization for parameter with multiple distributions in integrated circuit technology development Grant 6,907,379 - Wu , et al. June 14, 2	2005-06-14
Testing multiple levels in integrated circuit technology development Grant 6,875,560 - Steffan , et al. April 5, 2	2005-04-05
Determination of nonphotolithographic wafer process-splits in integrated circuit technology development Grant 6,864,107 - Erhardt , et al. March 8, 2	2005-03-08
Method of simultaneous display of die and wafer characterization in integrated circuit technology development Grant 6,815,233 - Erhardt , et al. November 9, 2	2004-11-09
Processing tester information by trellising in integrated circuit technology development Grant 6,766,265 - Shetty , et al. July 20, 2	2004-07-20
Processing Tester Information By Trellising In Integrated Circuit Technology Development App 20040122601 - Shetty, Shivananda S. ; et al.	2004-06-24

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