| Patent | Date |
|---|
Additional spacer for self-aligned contact for only high voltage FinFETs
Grant 10,991,689 - Zainuddin , et al. April 27, 2 | 2021-04-27 |
Additional Spacer For Self-aligned Contact For Only High Voltage Finfets
App 20200321332 - Zainuddin; Abu Naser M. ; et al. | 2020-10-08 |
Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same
Grant 10,396,078 - Holt , et al. A | 2019-08-27 |
Integrated Circuit Structure Including Laterally Recessed Source/drain Epitaxial Region And Method Of Forming Same
App 20180286863 - Holt; Judson R. ; et al. | 2018-10-04 |
Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same
Grant 10,020,307 - Holt , et al. July 10, 2 | 2018-07-10 |
Methods of modulating the morphology of epitaxial semiconductor material
Grant 9,953,873 - Chandra , et al. April 24, 2 | 2018-04-24 |
Modulation Of The Morphology Of Epitaxial Semiconductor Material
App 20170345719 - Chandra; Bhupesh ; et al. | 2017-11-30 |
Conformal buffer layer in source and drain regions of fin-type transistors
Grant 9,634,084 - Sheraw , et al. April 25, 2 | 2017-04-25 |
Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
Grant 9,287,399 - Chandra , et al. March 15, 2 | 2016-03-15 |
Faceted Intrinsic Epitaxial Buffer Layer For Reducing Short Channel Effects While Maximizing Channel Stress Levels
App 20150084096 - Chandra; Bhupesh ; et al. | 2015-03-26 |
Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
Grant 8,940,595 - Chandra , et al. January 27, 2 | 2015-01-27 |
Faceted Intrinsic Epitaxial Buffer Layer For Reducing Short Channel Effects While Maximizing Channel Stress Levels
App 20140264558 - Chandra; Bhupesh ; et al. | 2014-09-18 |
Filling narrow openings using ion beam etch
Grant 8,497,212 - Babich , et al. July 30, 2 | 2013-07-30 |
Filling Narrow Openings Using Ion Beam Etch
App 20120217590 - Babich; Katherina E. ; et al. | 2012-08-30 |
Method of reducing stacking faults through annealing
Grant 7,956,417 - Wang , et al. June 7, 2 | 2011-06-07 |
Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof
Grant 7,911,024 - Ho , et al. March 22, 2 | 2011-03-22 |
Stacking fault reduction in epitaxially grown silicon
Grant 7,893,493 - Wang , et al. February 22, 2 | 2011-02-22 |
Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices
Grant 7,871,893 - Costrini , et al. January 18, 2 | 2011-01-18 |
Method Of Reducing Stacking Faults Through Annealing
App 20100283089 - Wang; Yun-Yu ; et al. | 2010-11-11 |
Decoder for a stationary switch machine
Grant 7,820,501 - Wang , et al. October 26, 2 | 2010-10-26 |
Ultra-thin Soi Vertical Bipolar Transistors With An Inversion Collector On Thin-buried Oxide (box) For Low Substrate-bias Operation And Methods Thereof
App 20100207683 - Ho; Herbert L. ; et al. | 2010-08-19 |
Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof
Grant 7,763,518 - Ho , et al. July 27, 2 | 2010-07-27 |
Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation
Grant 7,691,716 - Ho , et al. April 6, 2 | 2010-04-06 |
Stacking fault reduction in epitaxially grown silicon
Grant 7,674,720 - Wang , et al. March 9, 2 | 2010-03-09 |
Method For Non-selective Shallow Trench Isolation Reactive Ion Etch For Patterning Hybrid-oriented Devices Compatible With High-performance Highly-integrated Logic Devices
App 20090189242 - Costrini; Gregory ; et al. | 2009-07-30 |
Dual Stress Liner Structure Having Substantially Planar Interface Between Liners And Related Method
App 20090090974 - Costrini; Gregory ; et al. | 2009-04-09 |
Copper contact via structure using hybrid barrier layer
Grant 7,498,256 - Knarr , et al. March 3, 2 | 2009-03-03 |
Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof
Grant 7,494,918 - Kim , et al. February 24, 2 | 2009-02-24 |
CMOS circuits including a passive element having a low end resistance
Grant 7,491,598 - Sheraw , et al. February 17, 2 | 2009-02-17 |
Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness
Grant 7,485,537 - Ho , et al. February 3, 2 | 2009-02-03 |
Stacking Fault Reduction In Epitaxially Grown Silicon
App 20080268609 - Wang; Yun-Yu ; et al. | 2008-10-30 |
VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BiCMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION
App 20080261371 - Ho; Herbert L. ; et al. | 2008-10-23 |
Ultra-thin Soi Vertical Bipolar Transistors With An Inversion Collector On Thin-buried Oxide (box) For Low Substrate-bias Operation And Methods Thereof
App 20080230869 - Ho; Herbert L. ; et al. | 2008-09-25 |
Ultra-thin Soi Vertical Bipolar Transistors With An Inversion Collector On Thin-buried Oxide (box) For Low Substrate-bias Operation And Methods Thereof
App 20080132025 - Ho; Herbert L. ; et al. | 2008-06-05 |
Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof
Grant 7,375,410 - Ho , et al. May 20, 2 | 2008-05-20 |
Cmos Circuits Including A Passive Element Having A Low End Resistance
App 20080096342 - Sheraw; Christopher D. ; et al. | 2008-04-24 |
CMOS circuits including a passive element having a low end resistance
Grant 7,361,959 - Sheraw , et al. April 22, 2 | 2008-04-22 |
Method Of Reducing Stacking Faults Through Annealing
App 20080087961 - Wang; Yun-Yu ; et al. | 2008-04-17 |
Semiconductor Structures Including Multiple Crystallographic Orientations And Methods For Fabrication Thereof
App 20080083952 - Kim; Byeong Y. ; et al. | 2008-04-10 |
Copper Contact Via Structure Using Hybrid Barrier Layer
App 20080042291 - Knarr; Randolph F. ; et al. | 2008-02-21 |
Stacking Fault Reduction In Epitaxially Grown Silicon
App 20080006876 - Wang; Yun-Yu ; et al. | 2008-01-10 |
Structure for improved diode ideality
Grant 7,227,204 - Maciejewski , et al. June 5, 2 | 2007-06-05 |
Cmos Circuits Incorporating Passive Elements Of Low Contact Resistance, And Methods Of Forming Same
App 20070120195 - Sheraw; Christopher D. ; et al. | 2007-05-31 |
Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation
App 20060263993 - Ho; Herbert L. ; et al. | 2006-11-23 |
Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation
Grant 7,115,965 - Ho , et al. October 3, 2 | 2006-10-03 |
Structure And Method For Improved Diode Ideality
App 20060180868 - Maciejewski; Edward P. ; et al. | 2006-08-17 |
Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation
App 20060043530 - Ho; Herbert L. ; et al. | 2006-03-02 |
Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof
App 20050184360 - Ho, Herbert L. ; et al. | 2005-08-25 |
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