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Patent applications and USPTO patent grants for Shephard; Philip G. III.The latest application filed is for "method and system for verifying performance of an array by simulating operation of edge cells in a full array model".
Patent | Date |
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Method and System for Verifying Performance of an Array by Simulating Operation of Edge Cells in a Full Array Model App 20070245279 - Agarwal; Vikas ;   et al. | 2007-10-18 |
Multiple mode approach to building static timing models for digital transistor circuits App 20070234253 - Soreff; Jeffrey P. ;   et al. | 2007-10-04 |
Test method for guaranteeing full stuck-at-fault coverage of a memory array App 20040199816 - Paredes, Jose A. ;   et al. | 2004-10-07 |
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