| Patent | Date |
|---|
Shallow trench isolation with self aligned PSG layer
Grant 5,729,043 - Shepard March 17, 1 | 1998-03-17 |
Packing density for flash memories
Grant 5,622,881 - Acocella , et al. April 22, 1 | 1997-04-22 |
Shallow trench isolation with self aligned PSG layer
Grant 5,616,513 - Shepard April 1, 1 | 1997-04-01 |
Method of making thin film transistor with a self-aligned bottom gate using diffusion from a dopant source layer
Grant 5,573,964 - Hsu , et al. November 12, 1 | 1996-11-12 |
Isolation structure using liquid phase oxide deposition
Grant 5,516,721 - Galli , et al. May 14, 1 | 1996-05-14 |
Method of making a DRAM cell with trench capacitor
Grant 5,395,786 - Hsu , et al. March 7, 1 | 1995-03-07 |
Method of forming integrated interconnect for very high density DRAMs
Grant 5,389,559 - Hsieh , et al. February 14, 1 | 1995-02-14 |
Method for forming a DRAM trench cell capacitor having a strap connection
Grant 5,384,277 - Hsu , et al. January 24, 1 | 1995-01-24 |
Method for forming capacitors with roughened single crystal plates
Grant 5,384,152 - Chu , et al. January 24, 1 | 1995-01-24 |
Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding
Grant 5,382,832 - Buti , et al. January 17, 1 | 1995-01-17 |
Method of fabricating a semiconductor device with raised diffusions and isolation
Grant 5,376,578 - Hsu , et al. December 27, 1 | 1994-12-27 |
Method for thinning SOI films having improved thickness uniformity
Grant 5,318,663 - Buti , et al. June 7, 1 | 1994-06-07 |
Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding
Grant 5,260,233 - Buti , et al. November 9, 1 | 1993-11-09 |
Capacitors with roughened single crystal plates
Grant 5,245,206 - Chu , et al. September 14, 1 | 1993-09-14 |
Inverse T-gate FET transistor with lightly doped source and drain region
Grant 5,241,203 - Hsu , et al. August 31, 1 | 1993-08-31 |
Method of forming an inverse T-gate FET transistor
Grant 5,120,668 - Hsu , et al. June 9, 1 | 1992-06-09 |
High performance sidewall emitter transistor
Grant 4,916,083 - Monkowski , et al. April 10, 1 | 1990-04-10 |
Mask using lithographic image size reduction
Grant 4,871,630 - Giammarco , et al. October 3, 1 | 1989-10-03 |
Lithographic image size reduction
Grant 4,707,218 - Giammarco , et al. November 17, 1 | 1987-11-17 |
Method for making submicron mask openings using sidewall and lift-off techniques
Grant 4,654,119 - Cook , et al. March 31, 1 | 1987-03-31 |
Self-aligned lateral bipolar transistors
Grant 4,641,170 - Ogura , et al. February 3, 1 | 1987-02-03 |
Submicron FET structure and method of making
Grant 4,636,834 - Shepard January 13, 1 | 1987-01-13 |
Method for forming recessed isolated regions
Grant 4,506,435 - Pliskin , et al. March 26, 1 | 1985-03-26 |
Method of making dense vertical FET's
Grant 4,407,058 - Fatula, Jr. , et al. October 4, 1 | 1983-10-04 |
Formation of bit lines for ram device
Grant 4,403,394 - Shepard , et al. September 13, 1 | 1983-09-13 |
Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
Grant 4,354,309 - Gardiner , et al. October 19, 1 | 1982-10-19 |
Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate
Grant 4,341,009 - Bartholomew , et al. July 27, 1 | 1982-07-27 |
Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon
Grant 4,251,571 - Garbarino , et al. February 17, 1 | 1981-02-17 |
Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers
Grant 4,249,968 - Gardiner , et al. February 10, 1 | 1981-02-10 |
Making semiconductor structure with improved phosphosilicate glass isolation
Grant 4,191,603 - Garbarino , et al. March 4, 1 | 1980-03-04 |
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