Shenoy; Narendra V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shenoy; Narendra V..The latest application filed is for "two-phase clock-stalling technique for error detection and error correction".

Company Profile

0.6.4

Shenoy; Narendra V. - Cupertino CA
Shenoy; Narendra V. - Bangalore IN
Shenoy; Narendra V. - Milpitas CA
Shenoy; Narendra V. - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Two-phase clock-stalling technique for error detection and error correction Grant 8,042,010 - Dartu , et al. October 18, 2	2011-10-18
Two-phase Clock-stalling Technique For Error Detection And Error Correction App 20100097107 - Dartu; Florentin ; et al.	2010-04-22
Identifying and improving robust designs using statistical timing analysis Grant 7,689,957 - Shenoy March 30, 2	2010-03-30
Identifying And Improving Robust Designs Using Statistical Timing Anaysis App 20090070714 - Shenoy; Narendra V.	2009-03-12
Method and apparatus for designing an integrated circuit using a mask-programmable fabric Grant 7,260,807 - Shenoy , et al. August 21, 2	2007-08-21
Method and apparatus for creating a mask-programmable architecture from standard cells Grant 7,100,142 - Kawa , et al. August 29, 2	2006-08-29
Method and apparatus for creating a mask-programmable architecture from standard cells App 20050229141 - Kawa, Jamil ; et al.	2005-10-13
Method and apparatus for designing an integrated circuit using a mask-programmable fabric App 20050132321 - Shenoy, Narendra V. ; et al.	2005-06-16
Adaptive cell separation and circuit changes driven by maximum capacitance rules Grant 6,397,169 - Shenoy , et al. May 28, 2	2002-05-28
Method for the physical placement of an integrated circuit adaptive to netlist changes Grant 6,378,114 - Shenoy , et al. April 23, 2	2002-04-23

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