Shenoy; Jayarama N.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shenoy; Jayarama N..The latest application filed is for "obfuscation-enhanced memory encryption".

Company Profile

2.14.6

Shenoy; Jayarama N. - San Jose CA
Shenoy; Jayarama N. - Fremont CA
Shenoy; Jayarama N. - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Obfuscation-enhanced memory encryption Grant 10,387,056 - Shenoy A	2019-08-20
Obfuscation-enhanced Memory Encryption App 20190121557 - Shenoy; Jayarama N.	2019-04-25
Obfuscation-enhanced Memory Encryption App 20190018603 - Shenoy; Jayarama N.	2019-01-17
Obfuscation-enhanced memory encryption Grant 10,180,804 - Shenoy Ja	2019-01-15
Obfuscation-enhanced memory encryption Grant 10,082,975 - Shenoy September 25, 2	2018-09-25
Obfuscation-enhanced Memory Encryption App 20180253243 - Shenoy; Jayarama N.	2018-09-06
Converting data signals in a multiple communication protocol system area network Grant 7,133,416 - Chamdani , et al. November 7, 2	2006-11-07
Method of making an electronic product including package-based inductor coupled to integrated circuit Grant 6,713,375 - Shenoy March 30, 2	2004-03-30
Method and apparatus for defining signal timing for an integrated circuit device App 20020157072 - Nishtala, Satyanarayana ; et al.	2002-10-24
Method of making a MOSFET structure having improved source/drain junction performance Grant 6,465,311 - Shenoy October 15, 2	2002-10-15
Technique to minimize crosstalk in electronic packages Grant 6,441,470 - Shenoy August 27, 2	2002-08-27
High performance chip/package inductor integration App 20020017699 - Shenoy, Jayarama N.	2002-02-14
High performance chip/package inductor integration Grant 6,310,386 - Shenoy October 30, 2	2001-10-30
Method of making a MOSFET structure having improved source/drain junction performance App 20010031536 - Shenoy, Jayarama N.	2001-10-18
MOSFET structure having improved source/drain junction performance Grant 6,239,472 - Shenoy May 29, 2	2001-05-29
Interconnect layout pattern for integrated circuit packages and the like Grant 6,198,635 - Shenoy , et al. March 6, 2	2001-03-06
Micro-electromechanical system and voltage shifter, method of synchronizing an electronic system and a micromechanical system of a micro-electromechanical system Grant 6,127,811 - Shenoy , et al. October 3, 2	2000-10-03
Apparatus for equalizing signal parameters in flip chip redistribution layers Grant 6,025,647 - Shenoy , et al. February 15, 2	2000-02-15
Flip chip circuit arrangement with redistribution layer that minimizes crosstalk Grant 5,994,766 - Shenoy , et al. November 30, 1	1999-11-30
Micro-electromechanical voltage shifter Grant 5,889,389 - Bothra , et al. March 30, 1	1999-03-30

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