| Patent | Date |
|---|
Memory cell and memory
Grant 9,496,047 - Yang , et al. November 15, 2 | 2016-11-15 |
Eight transistor (8T) write assist static random access memory (SRAM) cell
Grant 9,183,922 - Yang , et al. November 10, 2 | 2015-11-10 |
Image matching
Grant 9,075,826 - Shen , et al. July 7, 2 | 2015-07-07 |
Eight Transistor (8t) Write Assist Static Random Access Memory (sram) Cell
App 20140347916 - Yang; Jun ; et al. | 2014-11-27 |
Image Matching
App 20140341475 - Shen; Ju ; et al. | 2014-11-20 |
Memory Cell And Memory
App 20140056050 - YANG; Jun ; et al. | 2014-02-27 |
Simultaneous switching output noise estimation and reduction systems and methods
Grant 7,895,555 - West , et al. February 22, 2 | 2011-02-22 |
Register data retention systems and methods during reprogramming of programmable logic devices
Grant 7,876,125 - Tang , et al. January 25, 2 | 2011-01-25 |
Method and devices for storing a security key using programmable fuses
Grant 7,834,652 - Tang , et al. November 16, 2 | 2010-11-16 |
Input/output placement systems and methods to reduce simultaneous switching output noise
Grant 7,788,620 - Xue , et al. August 31, 2 | 2010-08-31 |
Methods and systems for storing a security key using programmable fuses
Grant 7,675,313 - Tang , et al. March 9, 2 | 2010-03-09 |
Reconfiguration of programmable logic devices
Grant 7,652,500 - Tang , et al. January 26, 2 | 2010-01-26 |
Programmable logic device with enhanced logic block architecture
Grant 7,573,291 - Agrawal , et al. August 11, 2 | 2009-08-11 |
Register data retention systems and methods during reprogramming of programmable logic devices
Grant 7,535,253 - Tang , et al. May 19, 2 | 2009-05-19 |
Reconfiguration of programmable logic devices
Grant 7,375,549 - Tang , et al. May 20, 2 | 2008-05-20 |
SERDES with programmable I/O architecture
Grant 7,327,160 - Agrawal , et al. February 5, 2 | 2008-02-05 |
Programmable logic device with enhanced logic block architecture
Grant 7,295,035 - Agrawal , et al. November 13, 2 | 2007-11-13 |
SERDES with programmable I/O architecture
Grant 7,208,975 - Agrawal , et al. April 24, 2 | 2007-04-24 |
Macrocells supporting a carry cascade
Grant 6,915,323 - Chang , et al. July 5, 2 | 2005-07-05 |
Programmable logic device with enhanced wide input product term cascading
Grant 6,903,573 - Cheng , et al. June 7, 2 | 2005-06-07 |
Non-volatile and reconfigurable programmable logic devices
Grant 6,828,823 - Tsui , et al. December 7, 2 | 2004-12-07 |
FIFO memory architecture
Grant 6,777,979 - Zhu , et al. August 17, 2 | 2004-08-17 |
Device and method with generic logic blocks
Grant 6,765,408 - Cheng , et al. July 20, 2 | 2004-07-20 |
Device and method with generic logic blocks
App 20040000928 - Cheng, Jason ; et al. | 2004-01-01 |
Method and structure for dynamic in-system programming
Grant 6,304,099 - Tang , et al. October 16, 2 | 2001-10-16 |
Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block)
Grant 6,128,770 - Agrawal , et al. October 3, 2 | 2000-10-03 |
Logic device (PLD) having direct connections between configurable logic blocks (CLBs) and configurable input/output blocks (IOBs)
Grant 5,740,069 - Agrawal , et al. April 14, 1 | 1998-04-14 |
Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer
Grant 5,587,921 - Agrawal , et al. December 24, 1 | 1996-12-24 |
Array of configurable logic blocks including cascadable lookup tables
Grant 5,586,044 - Agrawal , et al. December 17, 1 | 1996-12-17 |
Constant delay interconnect for coupling configurable logic blocks
Grant 5,490,074 - Agrawal , et al. February 6, 1 | 1996-02-06 |
Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output
Grant 5,469,368 - Agrawal , et al. November 21, 1 | 1995-11-21 |
Programmable gate array device having cascaded means for function definition
Grant 5,422,823 - Agrawal , et al. June 6, 1 | 1995-06-06 |
Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device
Grant 5,412,260 - Tsui , et al. May 2, 1 | 1995-05-02 |
Structure and method for implementing hierarchical routing pools in a programmable logic circuit
Grant 5,394,033 - Tsui , et al. February 28, 1 | 1995-02-28 |
Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
Grant 5,359,536 - Agrawal , et al. October 25, 1 | 1994-10-25 |
Structure and method for multiplexing pins for in-system programming
Grant 5,336,951 - Josephson , et al. August 9, 1 | 1994-08-09 |
Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
Grant 5,329,460 - Agrawal , et al. July 12, 1 | 1994-07-12 |
Programmable gate array with improved configurable logic block
Grant 5,260,881 - Agrawal , et al. November 9, 1 | 1993-11-09 |
Structure and method for multiplexing pins for in-system programming
Grant 5,237,218 - Josephson , et al. August 17, 1 | 1993-08-17 |
Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
Grant 5,233,539 - Agrawal , et al. August 3, 1 | 1993-08-03 |
Programmable gate array with improved interconnect structure
Grant 5,212,652 - Agrawal , et al. May 18, 1 | 1993-05-18 |
Output logic macrocell with enhanced functional capabilities
Grant 5,191,243 - Shen , et al. March 2, 1 | 1993-03-02 |
Sense amplifier with depletion transistor feedback
Grant 5,162,679 - Shen , et al. November 10, 1 | 1992-11-10 |
Integrated programmable logic device with control circuit to power down unused sense amplifiers
Grant 5,138,198 - Shen , et al. August 11, 1 | 1992-08-11 |
Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device
Grant 5,130,574 - Shen , et al. July 14, 1 | 1992-07-14 |
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