Shen; Jia-Pei
Patent Applications and Registrations
Patent applications and USPTO patent grants for Shen; Jia-Pei.The latest application filed is for "fast fourier transform circuit having partitioned memory for minimal latency during in-place computation".
- Shen; Jia-Pei - Stanford CA
- Shen, Jia-Pei - Kaohsiung TW
| Patent | Date |
|---|---|
| Minimum equalization error based channel estimator Grant 7,251,273 - Hwang , et al. July 31, 2 | 2007-07-31 |
| Fast fourier transform circuit having partitioned memory for minimal latency during in-place computation App 20050198092 - Shen, Jia-Pei ; et al. | 2005-09-08 |
| Minimum equalization error based channel estimator App 20040161066 - Hwang, Chien-Meen ; et al. | 2004-08-19 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 