| Patent | Date |
|---|
Mechanism for predicting and suppressing instruction replay in a processor
Grant 7,861,066 - Dhodapkar , et al. December 28, 2 | 2010-12-28 |
Method and apparatus for length decoding variable length instructions
Grant 7,818,542 - Shen , et al. October 19, 2 | 2010-10-19 |
Method and apparatus for length decoding and identifying boundaries of variable length instructions
Grant 7,818,543 - Shen , et al. October 19, 2 | 2010-10-19 |
Multiple-core processor with hierarchical microcode store
Grant 7,743,232 - Shen , et al. June 22, 2 | 2010-06-22 |
Distributed dispatch with concurrent, out-of-order dispatch
Grant 7,725,690 - Shen , et al. May 25, 2 | 2010-05-25 |
Redirect recovery cache that receives branch misprediction redirects and caches instructions to be dispatched in response to the redirects
Grant 7,685,410 - Shen , et al. March 23, 2 | 2010-03-23 |
Multiple-core Processor With Hierarchical Microcode Store
App 20090024836 - Shen; Gene W. ; et al. | 2009-01-22 |
Mechanism For Suppressing Instruction Replay In A Processor
App 20090024838 - Dhodapkar; Ashutosh S. ; et al. | 2009-01-22 |
Method and Apparatus for Length Decoding Variable Length Instructions
App 20090019263 - Shen; Gene W. ; et al. | 2009-01-15 |
Method and Apparatus for Length Decoding and Identifying Boundaries of Variable Length Instructions
App 20090019257 - Shen; Gene W. ; et al. | 2009-01-15 |
Distributed Dispatch with Concurrent, Out-of-Order Dispatch
App 20080195846 - Shen; Gene W. ; et al. | 2008-08-14 |
Redirect Recovery Cache
App 20080195844 - Shen; Gene W. ; et al. | 2008-08-14 |
MicroTLB and micro tag for reducing power in a processor
Grant 7,117,290 - Shen , et al. October 3, 2 | 2006-10-03 |
Method and system for architectural power estimation
Grant 7,051,300 - Shen , et al. May 23, 2 | 2006-05-23 |
Low power way-predicted cache
App 20050050278 - Meier, Stephan G. ; et al. | 2005-03-03 |
MicroTLB and micro TAG for reducing power in a processor
App 20050050277 - Shen, Gene W. ; et al. | 2005-03-03 |
Structure and method for instruction boundary machine state restoration
Grant 5,966,530 - Shen , et al. October 12, 1 | 1999-10-12 |
Method and apparatus for register management using issue sequence prior physical register and register association validity information
Grant 5,675,759 - Shebanow , et al. October 7, 1 | 1997-10-07 |
Processor structure and method for tracking floating-point exceptions
Grant 5,673,426 - Shen , et al. September 30, 1 | 1997-09-30 |
Processor structure and method for checkpointing instructions to maintain precise state
Grant 5,659,721 - Shen , et al. August 19, 1 | 1997-08-19 |
Processor structure and method for watchpoint of plural simultaneous unresolved branch evaluation
Grant 5,655,115 - Shen , et al. August 5, 1 | 1997-08-05 |
Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state
Grant 5,651,124 - Shen , et al. July 22, 1 | 1997-07-22 |
Processor structure and method for maintaining and restoring precise state at any instruction boundary
Grant 5,649,136 - Shen , et al. July 15, 1 | 1997-07-15 |
Processor structure and method for a time-out checkpoint
Grant 5,644,742 - Shen , et al. July 1, 1 | 1997-07-01 |
Cache controller for processing simultaneous cache accesses
Grant 5,598,550 - Shen , et al. January 28, 1 | 1997-01-28 |
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