loadpatents
name:-0.011138916015625
name:-0.028975009918213
name:-0.00066208839416504
Shemla; David Patent Filings

Shemla; David

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shemla; David.The latest application filed is for "vlan protocol".

Company Profile
0.30.11
  • Shemla; David - Kfar Ha Vradim N/A IL
  • Shemla; David - Kfar Havradim IL
  • Shemla, David - Kfar Havradlm IL
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Switching ethernet controller
Grant RE44,151 - Shemla , et al. April 16, 2
2013-04-16
VLAN protocol
Grant 8,416,783 - Medina , et al. April 9, 2
2013-04-09
Switching ethernet controller
Grant RE43,058 - Shemla , et al. January 3, 2
2012-01-03
VLAN Protocol
App 20110222544 - Medina; Eitan ;   et al.
2011-09-15
Method and apparatus for controlling the flow of packets through a network switch
Grant 8,005,104 - Medina , et al. August 23, 2
2011-08-23
VLAN protocol
Grant 7,957,388 - Medina , et al. June 7, 2
2011-06-07
Linking Cross Bar Controller
App 20100246595 - Medina; Eitan ;   et al.
2010-09-30
Switching ethernet controller providing packet routing
Grant RE41,464 - Willenz , et al. July 27, 2
2010-07-27
Linking cross bar controller
Grant 7,738,474 - Medina , et al. June 15, 2
2010-06-15
Bit clearing mechanism for an empty list
Grant 7,729,369 - Medina , et al. June 1, 2
2010-06-01
Vlan Protocol
App 20090296717 - Medina; Eitan ;   et al.
2009-12-03
VLAN protocol
Grant 7,573,882 - Medina , et al. August 11, 2
2009-08-11
Linking Cross Bar Controller
App 20090109989 - Medina; Eitan ;   et al.
2009-04-30
Linking cross bar controller
Grant 7,477,652 - Medina , et al. January 13, 2
2009-01-13
Bit clearing mechanism for an empty list
Grant 7,336,674 - Medina , et al. February 26, 2
2008-02-26
Switching ethernet controller
Grant RE39,514 - Shemla , et al. March 13, 2
2007-03-13
Bus protocol
Grant RE39,026 - Shemla , et al. March 21, 2
2006-03-21
Vlan protocol
App 20060039378 - Medina; Eitan ;   et al.
2006-02-23
VLAN protocol
Grant 6,975,581 - Medina , et al. December 13, 2
2005-12-13
Linking crossbar controller
Grant 6,967,962 - Medina , et al. November 22, 2
2005-11-22
Linking cross bar controller
App 20050232288 - Medina, Eitan ;   et al.
2005-10-20
Switching ethernet controller
Grant RE38,821 - Shemla , et al. October 11, 2
2005-10-11
Buffer switch having descriptor cache and method thereof
Grant 6,941,392 - Shemla , et al. September 6, 2
2005-09-06
Head of line blocking
App 20050041579 - Medina, Eitan ;   et al.
2005-02-24
Buffer switch having descriptor cache and method thereof
App 20050005037 - Shemla, David ;   et al.
2005-01-06
Head of line blocking
Grant 6,829,245 - Medina , et al. December 7, 2
2004-12-07
Network switch having descriptor cache and method thereof
Grant 6,738,838 - Shemla , et al. May 18, 2
2004-05-18
Bit clearing mechanism for an empty list
App 20040090975 - Medina, Eitan ;   et al.
2004-05-13
Bit clearing mechanism for an empty list
Grant 6,678,278 - Medina , et al. January 13, 2
2004-01-13
Network switch having descriptor cache and method thereof
App 20030200367 - Shemla, David ;   et al.
2003-10-23
Network switch having descriptor cache and method thereof
Grant 6,601,116 - Shemla , et al. July 29, 2
2003-07-29
Bit clearing mechanism for an empty list
App 20020009094 - Medina, Eitan ;   et al.
2002-01-24
Bit clearing mechanism for an empty list
Grant 6,240,065 - Medina , et al. May 29, 2
2001-05-29
Switching ethernet controller providing packet routing
Grant 5,999,981 - Willenz , et al. December 7, 1
1999-12-07
Bus protocol
Grant 5,930,261 - Shemla , et al. July 27, 1
1999-07-27
Switching ethernet controller
Grant 5,923,660 - Shemla , et al. July 13, 1
1999-07-13
Method and apparatus for managing packet memory
Grant 5,913,042 - Shemla , et al. June 15, 1
1999-06-15
Memory array comprised of multiple FIFO devices
Grant 5,809,557 - Shemla , et al. September 15, 1
1998-09-15
Synchronizing unit having two registers serially connected to one clocked elements and a latch unit for alternately activating the registers in accordance to clock signals
Grant 5,790,891 - Solt , et al. August 4, 1
1998-08-04

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed