Sheets, II; John Edward

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sheets, II; John Edward.The latest application filed is for "vertical stacking of field effect transistor structures for logic gates".

Company Profile

0.46.16

Sheets, II; John Edward - Zumbrota MN US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Vertical stacking of field effect transistor structures for logic gates Grant 8,754,417 - Christensen , et al. June 17, 2	2014-06-17
Implementing eDRAM stacked FET structure Grant 8,574,982 - Erickson , et al. November 5, 2	2013-11-05
Method and apparatus for measurement and control of photomask to substrate alignment Grant 8,536,587 - Granados , et al. September 17, 2	2013-09-17
FinFET with reduced gate to fin overlay sensitivity Grant 8,536,632 - Cheng , et al. September 17, 2	2013-09-17
Method and apparatus for measurement and control of photomask to substrate alignment Grant 8,535,393 - Granados , et al. September 17, 2	2013-09-17
FinFET with reduced gate to fin overlay sensitivity Grant 8,518,767 - Cheng , et al. August 27, 2	2013-08-27
Vertical Stacking of Field Effect Transistor Structures for Logic Gates App 20130001701 - Christensen; Todd Alan ; et al.	2013-01-03
Vertical stacking of field effect transistor structures for logic gates Grant 8,314,001 - Christensen , et al. November 20, 2	2012-11-20
Finfet With Reduced Gate To Fin Overlay Sensitivity App 20120146112 - Cheng; Kangguo ; et al.	2012-06-14
Enhanced field effect transistor Grant 8,138,054 - Allen , et al. March 20, 2	2012-03-20
Power distribution in a vertically integrated circuit Grant 8,105,940 - Christensen , et al. January 31, 2	2012-01-31
Method of enhancing on-chip inductance structure utilizing silicon through via technology Grant 8,079,134 - Maki , et al. December 20, 2	2011-12-20
Vertical Stacking of Field Effect Transistor Structures for Logic Gates App 20110248349 - Christensen; Todd Alan ; et al.	2011-10-13
Implementing Edram Stacked Fet Structure App 20110204428 - Erickson; Karl Robert ; et al.	2011-08-25
Implementing tamper evident and resistant detection through modulation of capacitance Grant 7,989,918 - Bartley , et al. August 2, 2	2011-08-02
Method and apparatus for measurement and control of photomask to substrate alignment Grant 7,935,546 - Granados , et al. May 3, 2	2011-05-03
Semiconductor scheme for reduced circuit area in a simplified process Grant 7,935,629 - Christensen , et al. May 3, 2	2011-05-03
Method And Apparatus For Measurement And Control Of Photomask To Substrate Alignment App 20110096329 - Granados; Axel Aguado ; et al.	2011-04-28
Method And Apparatus For Measurement And Control Of Photomask To Substrate Alignment App 20110096310 - Granados; Axel Aguado ; et al.	2011-04-28
Implementing eFuse resistance determination before initiating eFuse blow Grant 7,915,949 - Erickson , et al. March 29, 2	2011-03-29
Implementing APS voltage level activation with secondary chip in stacked-chip technology Grant 7,865,859 - Paone , et al. January 4, 2	2011-01-04
Enhanced Field Effect Transistor App 20100252868 - Allen; David Howard ; et al.	2010-10-07
Implementing eFuse Resistance Determination Before Initiating eFuse Blow App 20100232248 - Erickson; Karl Robert ; et al.	2010-09-16
Implementing Tamper Evident And Resistant Detection Through Modulation Of Capacitance App 20100187525 - Bartley; Gerald Keith ; et al.	2010-07-29
Power Distribution In A Vertically Integrated Circuit App 20100140808 - Christensen; Todd Alan ; et al.	2010-06-10
Method for improved power distribution in a three dimensional vertical integrated circuit Grant 7,727,887 - Christensen , et al. June 1, 2	2010-06-01
Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chips Grant 7,723,816 - Bartley , et al. May 25, 2	2010-05-25
Apparatus for improved power distribution in a three dimensional vertical integrated circuit Grant 7,701,064 - Christensen , et al. April 20, 2	2010-04-20
FinFET body contact structure Grant 7,696,565 - Donze , et al. April 13, 2	2010-04-13
Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction on Integrated Circuit Chips App 20100032799 - Bartley; Gerald Keith ; et al.	2010-02-11
Enhanced On-Chip Inductance Structure Utilizing Silicon Through Via Technology App 20100024202 - Maki; Andrew Benson ; et al.	2010-02-04
Implementing Reduced Hot-Spot Thermal Effects for SOI Circuits App 20100019385 - Bartley; Gerald Keith ; et al.	2010-01-28
Semiconductor scheme for reduced circuit area in a simplified process Grant 7,626,220 - Christensen , et al. December 1, 2	2009-12-01
Method and Apparatus for Measurement and Control of Photomask to Substrate Alignment App 20090195787 - Granados; Axel Aguado ; et al.	2009-08-06
Apparatus for Improved Power Distribution in a Three Dimensional Vertical Integrated Circuit App 20090108457 - Christensen; Todd Alan ; et al.	2009-04-30
Method for Improved Power Distribution in a Three Dimensional Vertical Integrated Circuit App 20090111214 - Christensen; Todd Alan ; et al.	2009-04-30
Aligning stacked chips using resistance assistance Grant 7,514,276 - Yearous , et al. April 7, 2	2009-04-07
Measurement of bias of a silicon area using bridging vertices on polysilicon shapes to create an electrical open/short contact structure Grant 7,336,086 - Donze , et al. February 26, 2	2008-02-26
Method and apparatus for improving performance margin in logic paths Grant 7,317,605 - Donze , et al. January 8, 2	2008-01-08
Semiconductor scheme for reduced circuit area in a simplified process Grant 7,317,217 - Christensen , et al. January 8, 2	2008-01-08
FinFET body contact structure Grant 7,241,649 - Donze , et al. July 10, 2	2007-07-10
Polysilicon conductor width measurement for 3-dimensional FETs Grant 7,227,183 - Donze , et al. June 5, 2	2007-06-05
Electrical open/short contact alignment structure for active region vs. gate region Grant 7,183,780 - Donze , et al. February 27, 2	2007-02-27
Method and apparatus for implementing silicon wafer chip carrier passive devices Grant 7,050,871 - Bartley , et al. May 23, 2	2006-05-23
Method and apparatus to reduce bias temperature instability (BTI) effects Grant 7,009,905 - Aipperspach , et al. March 7, 2	2006-03-07
Ring oscillator circuit for EDRAM/DRAM performance monitoring Grant 6,774,734 - Christensen , et al. August 10, 2	2004-08-10
Silicon-on-insulator (SOI) semiconductor structure for implementing transistor source connections using buried dual rail distribution Grant 6,670,716 - Christensen , et al. December 30, 2	2003-12-30
Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices Grant 6,667,518 - Christensen , et al. December 23, 2	2003-12-23
Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices Grant 6,645,796 - Christensen , et al. November 11, 2	2003-11-11
SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies Grant 6,635,518 - Aipperspach , et al. October 21, 2	2003-10-21
Method for implementing SOI transistor source connections using buried dual rail distribution Grant 6,498,057 - Christensen , et al. December 24, 2	2002-12-24
Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices Grant 6,492,244 - Christensen , et al. December 10, 2	2002-12-10
Implementing contacts for bodies of semiconductor-on-insulator transistors Grant 6,429,099 - Christensen , et al. August 6, 2	2002-08-06
Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors Grant 6,287,901 - Christensen , et al. September 11, 2	2001-09-11
Buried patterned conductor planes for semiconductor-on-insulator integrated circuit Grant 6,121,659 - Christensen , et al. September 19, 2	2000-09-19
Driver circuit for providing reduced AC defects Grant 6,043,689 - Sheets, II , et al. March 28, 2	2000-03-28

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