Sheaffer; Gad S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sheaffer; Gad S..The latest application filed is for "augmented reality alteration detector".

Company Profile

1.29.26

Sheaffer; Gad S. - Haifa IL
Sheaffer; Gad S - Haifa IL
Sheaffer; Gad S. - Beaverton OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Augmented reality alteration detector Grant 10,229,523 - Sheaffer , et al.	2019-03-12
Augmented Reality Alteration Detector App 20170206692 - Sheaffer; Gad S. ; et al.	2017-07-20
Augmented reality alteration detector Grant 9,626,773 - Sheaffer , et al. April 18, 2	2017-04-18
Scheduling computing tasks for multi-processor systems based on resource requirements Grant 9,619,298 - Sheaffer , et al. April 11, 2	2017-04-11
Instance monitor Grant 9,430,350 - Ur , et al. August 30, 2	2016-08-30
Remotely Controlled Crowd-sourced Media Capture App 20160234287 - SHEAFFER; Gad S. ; et al.	2016-08-11
Remotely controlled crowd-sourced media capture Grant 9,350,909 - Sheaffer , et al. May 24, 2	2016-05-24
Scheduling Computing Tasks For Multi-processor Systems App 20150150019 - Sheaffer; Gad S. ; et al.	2015-05-28
Augmented Reality Alteration Detector App 20150070388 - Sheaffer; Gad S. ; et al.	2015-03-12
Instance Monitor App 20140289392 - Ur; Shmuel ; et al.	2014-09-25
Remotely Controlled Crowd-sourced Media Capture App 20140218549 - Sheaffer; Gad S. ; et al.	2014-08-07
Malware Attack Prevention Using Block Code Permutation App 20140165197 - Ur; Shmuel ; et al.	2014-06-12
Technique for using memory attributes Grant 8,560,781 - Jacobson , et al. October 15, 2	2013-10-15
Method and system of handling non-aligned memory accesses Grant 8,359,433 - Sheaffer January 22, 2	2013-01-22
Methods And Apparatuses For Re-ordering Data App 20120047344 - Sheaffer; Gad S.	2012-02-23
Method And System Of Handling Non-aligned Memory Accesses App 20120047311 - Sheaffer; Gad S.	2012-02-23
Technique For Using Memory Attributes App 20110264866 - Jacobson; Quinn A. ; et al.	2011-10-27
Technique for using memory attributes Grant 7,991,965 - Jacobson , et al. August 2, 2	2011-08-02
Method and apparatus for varying energy per instruction according to the amount of available parallelism Grant 7,437,581 - Grochowski , et al. October 14, 2	2008-10-14
Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs Grant 7,257,728 - Wilcox , et al. August 14, 2	2007-08-14
Technique for using memory attributes App 20070186055 - Jacobson; Quinn A. ; et al.	2007-08-09
Method and apparatus for varying energy per instruction according to the amount of available parallelism App 20060095807 - Grochowski; Edward ; et al.	2006-05-04
Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs Grant 7,007,187 - Wilcox , et al. February 28, 2	2006-02-28
Instruction set extension using operand bearing NOP instructions App 20050289325 - Sheaffer, Gad S.	2005-12-29
Method and system to overlap pointer load cache misses Grant 6,965,962 - Sheaffer November 15, 2	2005-11-15
Instruction set extension using operand bearing NOP instructions Grant 6,957,321 - Sheaffer October 18, 2	2005-10-18
Pre-steering register renamed instructions to execution unit associated locations in instruction cache Grant 6,944,750 - Sheaffer September 13, 2	2005-09-13
Add-compare-select accelerator using pre-compare-select-add operation Grant 6,928,605 - Sheaffer August 9, 2	2005-08-09
Add-compare-select accelerator using pre-compare-select-add operation App 20050172210 - Sheaffer, Gad S.	2005-08-04
Buffer pre-loading for memory service interruptions Grant 6,859,851 - Sheaffer February 22, 2	2005-02-22
Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs App 20040236979 - Wilcox, Jeffrey R. ; et al.	2004-11-25
Methods and apparatus for gathering and scattering data associated with a single-instruction-multiple-data (SIMD) operation App 20040236920 - Sheaffer, Gad S.	2004-11-25
Method and apparatus for pre-processing instructions for a processor Grant 6,779,104 - Sheaffer August 17, 2	2004-08-17
Eliminating register reads and writes in a scheduled instruction cache App 20040128482 - Sheaffer, Gad S.	2004-07-01
Method and system to overlap pointer load cache misses App 20040117555 - Sheaffer, Gad S.	2004-06-17
Method and apparatus for performing sequential executions of elements in cooperation with a transform App 20040088525 - D'Sa, Reynold V. ; et al.	2004-05-06
Reducing the length of lower level instructions by splitting and recombining an immediate Grant 6,732,257 - Sheaffer May 4, 2	2004-05-04
Method and apparatus for performing sequential executions of elements in cooperation with a transform Grant 6,715,064 - D'Sa , et al. March 30, 2	2004-03-30
Method for performing complex number multiplication and fast fourier App 20040003017 - Dagan, Amit ; et al.	2004-01-01
Instruction set extension using operand bearing NOP instructions App 20030236965 - Sheaffer, Gad S.	2003-12-25
Method and system to perform complex number multiplications and calculations App 20030212728 - Dagan, Amit ; et al.	2003-11-13
Add-compare-select accelerator using pre-compare-select-add operation App 20030188244 - Sheaffer, Gad S.	2003-10-02
Multiply-accumulate accelerator with data re-use App 20030145030 - Sheaffer, Gad S.	2003-07-31
Method and apparatus for pre-processing instructions for a processor App 20030135714 - Sheaffer, Gad S.	2003-07-17
Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters Grant 6,594,754 - Jourdan , et al. July 15, 2	2003-07-15
Method and apparatus for pre-processing instructions for a processor Grant 6,539,471 - Sheaffer March 25, 2	2003-03-25
Method And Apparatus For Pre-processing Instructions For A Processor App 20020035677 - SHEAFFER, GAD S.	2002-03-21
Method and apparatus for constructing a pre-scheduled instruction cache Grant 6,351,802 - Sheaffer February 26, 2	2002-02-26
System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units Grant 6,055,630 - D'Sa , et al. April 25, 2	2000-04-25
Method of branch prediction using loop counters Grant 5,909,573 - Sheaffer June 1, 1	1999-06-01
Computer for performing non-restoring division Grant 5,818,745 - Sheaffer October 6, 1	1998-10-06
Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor Grant 5,790,822 - Sheaffer , et al. August 4, 1	1998-08-04
Instruction dependency chain indentifier Grant 5,710,902 - Sheaffer , et al. January 20, 1	1998-01-20

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