loadpatents
name:-0.058691024780273
name:-0.019254922866821
name:-0.026787996292114
She; Yong Patent Filings

She; Yong

Patent Applications and Registrations

Patent applications and USPTO patent grants for She; Yong.The latest application filed is for "integrated circuit package with glass spacer".

Company Profile
23.14.25
  • She; Yong - Songjiang CN
  • She; Yong - Shanghai CN
  • She; Yong - Folsom CA
  • She; Yong - Minghang CN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated Circuit Package With Glass Spacer
App 20220254757 - Guo; Mao ;   et al.
2022-08-11
Power Enhanced Stacked Chip Scale Package Solution With Integrated Die Attach Film
App 20220230995 - Xu; Zhijun ;   et al.
2022-07-21
Integrated circuit package with glass spacer
Grant 11,393,788 - Guo , et al. July 19, 2
2022-07-19
Joint Connection Of Corner Non-critical To Function (nctf) Ball For Bga Solder Joint Reliability (sjr) Enhancement
App 20220122907 - TANG; Xiaoying ;   et al.
2022-04-21
Power enhanced stacked chip scale package solution with integrated die attach film
Grant 11,302,671 - Xu , et al. April 12, 2
2022-04-12
Film In Substrate For Releasing Z Stack-up Constraint
App 20220093568 - HU; Jianfeng ;   et al.
2022-03-24
Die Stack With Reduced Warpage
App 20220020704 - She; Yong ;   et al.
2022-01-20
Integrated Circuit Package With Glass Spacer
App 20210280558 - Guo; Mao ;   et al.
2021-09-09
Electronic Device Package
App 20210265305 - Ding; Zhicheng ;   et al.
2021-08-26
Die stack with reduced warpage
Grant 11,081,451 - She , et al. August 3, 2
2021-08-03
Stair-stacked dice device in a system in package, and methods of making same
Grant 10,991,679 - Ding , et al. April 27, 2
2021-04-27
Interconnect Structure Fabricated Using Lithographic And Deposition Processes
App 20210057326 - DING; Zhicheng ;   et al.
2021-02-25
Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same
Grant 10,930,622 - Ding , et al. February 23, 2
2021-02-23
Method, apparatus and system to interconnect packaged integrated circuit dies
Grant 10,910,347 - She , et al. February 2, 2
2021-02-02
Stair-stacked Dice Device In A System In Package, And Methods Of Making Same
App 20200402961 - Ding; Zhicheng ;   et al.
2020-12-24
Pre-molded active IC of passive components to miniaturize system in package
Grant 10,872,832 - Guo , et al. December 22, 2
2020-12-22
Prepackaged Stair-stacked Memory Module In A Chip Scale System In Package, And Methods Of Making Same
App 20200357773 - Ding; Zhicheng ;   et al.
2020-11-12
Stacked Die Semiconductor Package Spacer Die
App 20200350227 - Gogineni; Sireesha ;   et al.
2020-11-05
Stair-stacked dice device in a system in package, and methods of making same
Grant 10,770,434 - Ding , et al. Sep
2020-09-08
Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same
Grant 10,727,208 - Ding , et al.
2020-07-28
Power Enhanced Stacked Chip Scale Package Solution With Integrated Die Attach Film
App 20200227387 - Xu; Zhijun ;   et al.
2020-07-16
Die Stack With Reduced Warpage
App 20200051929 - She; Yong ;   et al.
2020-02-13
Techniques For Windowed Substrate Integrated Circuit Packages
App 20190355700 - Tan; Aiping ;   et al.
2019-11-21
Method, Apparatus And System To Interconnect Packaged Integrated Circuit Dies
App 20190341372 - She; Yong ;   et al.
2019-11-07
Wire bond connection with intermediate contact structure
Grant 10,438,916 - She O
2019-10-08
Vertical Bond-wire Stacked Chip-scale Package With Application-specific Integrated Circuit Die On Stack, And Methods Of Making S
App 20190273037 - Ding; Zhicheng ;   et al.
2019-09-05
Method, apparatus and system to interconnect packaged integrated circuit dies
Grant 10,396,055 - She , et al. A
2019-08-27
Prepackaged Stair-stacked Memory Module In A Chip Scale System In Package, And Methods Of Making Same
App 20190229092 - Ding; Zhicheng ;   et al.
2019-07-25
Stair-stacked Dice Device In A System In Package, And Methods Of Making Same
App 20190214370 - Ding; Zhicheng ;   et al.
2019-07-11
3D package having edge-aligned die stack with direct inter-die wire connections
Grant 10,332,899 - Xu , et al.
2019-06-25
3d Package Having Edge-aligned Die Stack With Direct Inter-die Wire Connections
App 20190103409 - XU; Yi ;   et al.
2019-04-04
Wire Bond Connection With Intermediate Contact Structure
App 20190051627 - SHE; Yong
2019-02-14
Method, Apparatus And System To Interconnect Packaged Integrated Circuit Dies
App 20190019777 - SHE; Yong ;   et al.
2019-01-17
Pre-molded Active Ic Of Passive Components To Miniaturize System In Package
App 20180331004 - GUO; Mao ;   et al.
2018-11-15
Semiconductor Packages Having A Fiducial Marker And Methods For Aligning Tools Relative To The Fiducial Marker
App 20180096946 - Meyers; John G. ;   et al.
2018-04-05
Electronic device package
Grant 9,859,255 - Yoon , et al. January 2, 2
2018-01-02
Flexible system-in-package solutions for wearable devices
Grant 9,778,688 - Tang , et al. October 3, 2
2017-10-03
Flexible System-in-package Solutions For Wearable Devices
App 20160327977 - Tang; Jiamiao ;   et al.
2016-11-10
Thermoplastic molding material for electronic packaging
App 20060275569 - Mishra; Sanjay Braj ;   et al.
2006-12-07

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