Shaw; Ching-Hao

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shaw; Ching-Hao.The latest application filed is for "circuit having capacitor coupled with memory element".

Company Profile

0.10.7

Shaw; Ching-Hao - San Jose CA
Shaw; Ching-Hao - Hsin-Chu TW
Shaw; Ching-Hao - Plano TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuit having capacitor coupled with memory element Grant 9,484,067 - Shaw , et al. November 1, 2	2016-11-01
Circuit Having Capacitor Coupled With Memory Element App 20140339618 - SHAW; Ching-Hao ; et al.	2014-11-20
Providing capacitors to improve radiation hardening in memory elements Grant 8,824,226 - Shaw , et al. September 2, 2	2014-09-02
Providing Capacitors To Improve Radiation Hardening In Memory Elements App 20100254069 - SHAW; Ching-Hao ; et al.	2010-10-07
Method and system for setup/hold characterization in sequential cells Grant 7,795,939 - Chen , et al. September 14, 2	2010-09-14
Method and System for Setup/Hold Characterization in Sequential Cells App 20100164583 - Chen; Ker-Min ; et al.	2010-07-01
Standard cell back bias architecture Grant 7,314,788 - Shaw , et al. January 1, 2	2008-01-01
Very fine-grain voltage island integrated circuit Grant 7,247,894 - Hou , et al. July 24, 2	2007-07-24
Standard cell back bias architecture App 20060134853 - Shaw; Ching-Hao ; et al.	2006-06-22
Very fine-grain voltage island integrated circuit App 20050242375 - Hou, Cliff ; et al.	2005-11-03
Standard cell back bias architecture App 20050051801 - Shaw, Ching-Hao ; et al.	2005-03-10
Efficient source diffusion interconnect, MOS transistor and standard cell layout utilizing same Grant 6,849,904 - Tien , et al. February 1, 2	2005-02-01
Efficient source diffusion interconnect, MOS transistor and standard cell layout utilizing same App 20040211983 - Tien, Li-Chun ; et al.	2004-10-28
Base cell for BiCMOS and CMOS gate arrays Grant 5,684,311 - Shaw November 4, 1	1997-11-04
Comprehensive logic circuit layout system Grant 5,461,577 - Shaw , et al. October 24, 1	1995-10-24
Comprehensive logic circuit layout system Grant 5,150,309 - Shaw , et al. September 22, 1	1992-09-22

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.