| Patent | Date |
|---|
Fabricating Sub-Lithographic Devices
App 20200409272 - Sharma; Gian ; et al. | 2020-12-31 |
Fabricating Devices with Reduced Isolation Regions
App 20200409273 - Levi; Amitay ; et al. | 2020-12-31 |
Adjustable current selectors
Grant 10,854,260 - Kim , et al. December 1, 2 | 2020-12-01 |
Dual threshold voltage devices having a first transistor and a second transistor
Grant 10,770,510 - Sharma , et al. Sep | 2020-09-08 |
Methods of fabricating dual threshold voltage devices
Grant 10,770,561 - Sharma , et al. Sep | 2020-09-08 |
Patterning of high density small feature size pillar structures
Grant 10,614,867 - Sharma , et al. | 2020-04-07 |
Patterning Of High Density Small Feature Size Pillar Structures
App 20200043537 - Sharma; Gian ; et al. | 2020-02-06 |
Dual gate memory devices
Grant 10,497,415 - Kim , et al. De | 2019-12-03 |
Perpendicular magnetic tunnel junction memory cells having shared source contacts
Grant 10,460,778 - Kim , et al. Oc | 2019-10-29 |
Methods of Fabricating Dual Threshold Voltage Devices
App 20190311956 - Sharma; Gian ; et al. | 2019-10-10 |
Annular vertical Si etched channel MOS devices
Grant 10,438,999 - Sharma , et al. O | 2019-10-08 |
Adjustable Current Selectors
App 20190287596 - Kim; Kuk-Hwan ; et al. | 2019-09-19 |
Fabrication methods of forming annular vertical SI etched channel MOS devices
Grant 10,355,047 - Sharma , et al. July 16, 2 | 2019-07-16 |
Dual Threshold Voltage Devices
App 20190214431 - Sharma; Gian ; et al. | 2019-07-11 |
Dual Gate Memory Devices
App 20190214069 - Kim; Kuk-Hwan ; et al. | 2019-07-11 |
Cylindrical vertical SI etched channel 3D switching devices
Grant 10,347,311 - Sharma , et al. July 9, 2 | 2019-07-09 |
Fabrication methods of forming cylindrical vertical SI etched channel 3D switching devices
Grant 10,347,822 - Sharma , et al. July 9, 2 | 2019-07-09 |
Cylindrical Vertical Si Etched Channel 3d Switching Devices
App 20190206461 - Sharma; Gian ; et al. | 2019-07-04 |
Annular Vertical Si Etched Channel Mos Devices
App 20190206938 - Sharma; Gian ; et al. | 2019-07-04 |
Fabrication Methods Of Forming Annular Vertical Si Etched Channel Mos Devices
App 20190206937 - Sharma; Gian ; et al. | 2019-07-04 |
Perpendicular Magnetic Tunnel Junction Memory Cells Having Shared Source Contacts
App 20190206463 - Kim; Kuk-Hwan ; et al. | 2019-07-04 |
Fabrication Methods Of Forming Cylindrical Vertical Si Etched Channel 3d Switching Devices
App 20190207081 - Sharma; Gian ; et al. | 2019-07-04 |
Adjustable current selectors
Grant 10,319,424 - Kim , et al. | 2019-06-11 |
Methods of fabricating contacts for cylindrical devices
Grant 10,192,787 - Sharma , et al. Ja | 2019-01-29 |
Methods of fabricating dual threshold voltage devices with stacked gates
Grant 10,192,788 - Sharma , et al. Ja | 2019-01-29 |
Dual threshold voltage devices with stacked gates
Grant 10,192,984 - Sharma , et al. Ja | 2019-01-29 |
Methods of fabricating dual threshold voltage devices
Grant 10,192,789 - Sharma , et al. Ja | 2019-01-29 |
Buried tap for a vertical transistor used with a perpendicular magnetic tunnel junction (PMTJ)
Grant 10,186,551 - Kim , et al. Ja | 2019-01-22 |
Method of planarizing a semiconductor die
Grant 6,969,687 - Levi , et al. November 29, 2 | 2005-11-29 |
Method of planarizing a semiconductor die
App 20040152397 - Levi, Amitay ; et al. | 2004-08-05 |
Method for forming a sublithographic opening in a semiconductor process
Grant 6,756,284 - Sharma June 29, 2 | 2004-06-29 |
Method for forming a sublithographic opening in a semiconductor process
App 20040053475 - Sharma, Gian | 2004-03-18 |
Method of planarizing a semiconductor die
Grant 6,703,318 - Levi , et al. March 9, 2 | 2004-03-09 |
Hybrid trench isolation technology for high voltage isolation using thin field oxide in a semiconductor process
Grant 6,699,772 - Sharma March 2, 2 | 2004-03-02 |
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