Shaheed; M. Reaz
Patent Applications and Registrations
Patent applications and USPTO patent grants for Shaheed; M. Reaz.The latest application filed is for "method of fabricating a mosfet transistor having an anti-halo for modifying narrow width device performance".
- Shaheed; M. Reaz - Portland OR
- Shaheed; M. Reaz - Beaverton OR
| Patent | Date |
|---|---|
| Methods of manufacturing a stressed MOS transistor structure Grant 7,338,847 - Shaheed , et al. March 4, 2 | 2008-03-04 |
| Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance App 20070145495 - Curello; Giuseppe ; et al. | 2007-06-28 |
| Strained field effect transistors App 20060292776 - Jin; Been-Yih ; et al. | 2006-12-28 |
| Silicon germanium heterojunction bipolar transistor with step-up carbon profile Grant 6,972,441 - Shaheed December 6, 2 | 2005-12-06 |
| Methods of manufacturing a stressed MOS transistor structure App 20050104057 - Shaheed, M. Reaz ; et al. | 2005-05-19 |
| Increasing stress-enhanced drive current in a MOS transistor Grant 6,870,179 - Shaheed , et al. March 22, 2 | 2005-03-22 |
| Increasing stress-enhanced drive current in a MOS transistor App 20040188670 - Shaheed, M. Reaz ; et al. | 2004-09-30 |
| Silicon germanium heterojunction bipolar transistor with step-up carbon profile App 20040099880 - Shaheed, M. Reaz | 2004-05-27 |
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