Shah; Mahesh K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shah; Mahesh K..The latest application filed is for "semiconductor package having an isolation wall to reduce electromagnetic coupling".

Company Profile

8.22.21

Shah; Mahesh K. - Scottsdale AZ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Microelectronic components having integrated heat dissipation posts and systems including the same Grant 10,861,764 - Viswanathan , et al. December 8, 2	2020-12-08
Packaged microelectronic component mounting using sinter attachment Grant 10,806,021 - Viswanathan , et al. October 13, 2	2020-10-13
Semiconductor package having an isolation wall to reduce electromagnetic coupling Grant 10,630,243 - Szymanowski , et al.	2020-04-21
Semiconductor Package Having An Isolation Wall To Reduce Electromagnetic Coupling App 20200067460 - Szymanowski; Margaret A. ; et al.	2020-02-27
Semiconductor package having an isolation wall to reduce electromagnetic coupling Grant 10,476,442 - Szymanowski , et al. Nov	2019-11-12
Packaged Microelectronic Component Mounting Using Sinter Attachment App 20190342988 - Viswanathan; Lakshminarayan ; et al.	2019-11-07
Microelectronic modules including thermal extension levels and methods for the fabrication thereof Grant 10,440,813 - Li , et al. O	2019-10-08
Packaged microelectronic component mounting using sinter attachment Grant 10,405,417 - Viswanathan , et al. Sep	2019-09-03
Microelectronic Components Having Integrated Heat Dissipation Posts And Systems Including The Same App 20190206759 - Viswanathan; Lakshminarayan ; et al.	2019-07-04
Microelectronic components having integrated heat dissipation posts, systems including the same, and methods for the fabrication thereof Grant 10,269,678 - Viswanathan , et al.	2019-04-23
High power semiconductor package subsystems Grant 10,211,177 - Viswanathan , et al. Feb	2019-02-19
Semiconductor Package Having An Isolation Wall To Reduce Electromagnetic Coupling App 20190028063 - Szymanowski; Margaret A. ; et al.	2019-01-24
Packaged Microelectronic Component Mounting Using Sinter Attachment App 20180317312 - Viswanathan; Lakshminarayan ; et al.	2018-11-01
Semiconductor package having an isolation wall to reduce electromagnetic coupling Grant 10,110,170 - Szymanowski , et al. October 23, 2	2018-10-23
Radio frequency devices with surface-mountable capacitors for decoupling and methods thereof Grant 9,800,208 - Shah , et al. October 24, 2	2017-10-24
High Power Semiconductor Package Subsystems App 20170271292 - Viswanathan; Lakshminarayan ; et al.	2017-09-21
High power semiconductor package subsystems Grant 9,673,162 - Viswanathan , et al. June 6, 2	2017-06-06
Semiconductor Package Having An Isolation Wall To Reduce Electromagnetic Coupling App 20170005621 - Szymanowski; Margaret A. ; et al.	2017-01-05
Solder wettable flanges and devices and systems incorporating solder wettable flanges Grant 9,538,659 - Viswanathan , et al. January 3, 2	2017-01-03
Semiconductor devices, semiconductor device packages, and packaging techniques for impedance matching and/or low frequency terminations Grant 9,484,222 - Ladhani , et al. November 1, 2	2016-11-01
Semiconductor package having an isolation wall to reduce electromagnetic coupling Grant 9,450,547 - Szymanowski , et al. September 20, 2	2016-09-20
Radio Frequency Devices With Surface-mountable Capacitors For Decoupling And Methods Thereof App 20160164471 - SHAH; Mahesh K. ; et al.	2016-06-09
Radio frequency devices with surface-mountable capacitors for decoupling and methods thereof Grant 9,300,254 - Shah , et al. March 29, 2	2016-03-29
Radio Frequency Devices With Surface-mountable Capacitors For Decoupling And Methods Thereof App 20150381117 - SHAH; Mahesh K. ; et al.	2015-12-31
Semiconductor Devices, Semiconductor Device Packages, And Packaging Techniques For Impedance Matching And/or Low Frequency Terminations App 20150235933 - Ladhani; Hussain H. ; et al.	2015-08-20
Semiconductor Package Having An Isolation Wall To Reduce Electromagnetic Coupling App 20150170986 - Szymanowski; Margaret A. ; et al.	2015-06-18
Solder Wettable Flanges And Devices And Systems Incorporating Solder Wettable Flanges App 20150055310 - VISWANATHAN; LAKSHMINARAYAN ; et al.	2015-02-26
High Power Semiconductor Package Subsystems App 20140070397 - Viswanathan; Lakshminarayan ; et al.	2014-03-13
Semiconductor device with a buffer region with tightly-packed filler particles Grant 7,701,074 - Condie , et al. April 20, 2	2010-04-20
Semiconductor Device With A Buffer Region With Tightly-packed Filler Particles App 20090001614 - Condie; Brian W. ; et al.	2009-01-01
Semiconductor device with reduced package cross-talk and loss Grant 7,435,625 - Condie , et al. October 14, 2	2008-10-14
Plastic packaged device with die interface layer Grant 7,432,133 - Condie , et al. October 7, 2	2008-10-07
Chemical die singulation technique Grant 7,332,414 - Condie , et al. February 19, 2	2008-02-19
Semiconductor device with improved encapsulation App 20070090545 - Condie; Brian W. ; et al.	2007-04-26
Semiconductor device with reduced package cross-talk and loss App 20070090542 - Condie; Brian W. ; et al.	2007-04-26
Plastic packaged device with die interface layer App 20070090543 - Condie; Brian W. ; et al.	2007-04-26
Chemical die singulation technique App 20060292827 - Condie; Brian W. ; et al.	2006-12-28
Method for making a sculptured diaphragm Grant 5,888,412 - Sooriakumar , et al. March 30, 1	1999-03-30

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