Shah; Hemen R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shah; Hemen R..The latest application filed is for "critical path redundant logic for mitigation of hardware across chip variation".

Company Profile

0.8.6

Shah; Hemen R. - South Burlington VT
Shah; Hemen R. - US
Shah; Hemen R. - Essex Jct. VT
Shah; Hemen R. - Essex Jct

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and systems of powering on integrated circuit Grant 8,016,482 - Arsovski , et al. September 13, 2	2011-09-13
Critical path redundant logic for mitigation of hardware across chip variation Grant 7,898,286 - Arsovski , et al. March 1, 2	2011-03-01
Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design Grant 7,823,107 - Arsovski , et al. October 26, 2	2010-10-26
Critical Path Redundant Logic for Mitigation of Hardware Across Chip Variation App 20100201377 - ARSOVSKI; Igor ; et al.	2010-08-12
Design structures of powering on integrated circuit Grant 7,716,007 - Arsovski , et al. May 11, 2	2010-05-11
Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design Grant 7,643,591 - Arsovski , et al. January 5, 2	2010-01-05
Transition Balancing For Noise Reduction/Di/Dt Reduction During Design, Synthesis, and Physical Design App 20090106724 - Arsovski; Igor ; et al.	2009-04-23
Design structures, method and systems of powering on integrated circuit Grant 7,483,806 - Arsovski , et al. January 27, 2	2009-01-27
Method And Systems Of Powering On Integrated Circuit App 20090022203 - Arsovski; Igor ; et al.	2009-01-22
Structures Of Powering On Integrated Circuit App 20090024972 - Arsovski; Igor ; et al.	2009-01-22
Design Structures, Method And Systems Of Powering On Integrated Circuit App 20090021085 - Arsovski; Igor ; et al.	2009-01-22
TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DESIGN, SYNTHESIS, AND PHYSICAL DESIGN App 20080043890 - Arsovski; Igor ; et al.	2008-02-21
No latency pipeline Grant 5,532,970 - Butler , et al. July 2, 1	1996-07-02
High performance extended data out Grant 5,490,114 - Butler , et al. February 6, 1	1996-02-06

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