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name:-0.013633966445923
name:-0.022459030151367
name:-0.00041317939758301
Sessions; D. C. Patent Filings

Sessions; D. C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sessions; D. C..The latest application filed is for "capless voltage regulator using clock-frequency feed forward control".

Company Profile
0.23.14
  • Sessions; D. C. - Phoenix AZ
  • Sessions; D C - Phoenix AZ
  • Sessions; D. C. - Phoeniz AZ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Capless voltage regulator using clock-frequency feed forward control
Grant 9,515,549 - Sessions December 6, 2
2016-12-06
Using low voltage regulator to supply power to a source-biased power domain
Grant 8,970,190 - Muha , et al. March 3, 2
2015-03-03
Capless Voltage Regulator Using Clock-Frequency Feed Forward Control
App 20140266317 - Sessions; D.C.
2014-09-18
Dynamic state configuration restore
Grant 8,825,912 - Lahti , et al. September 2, 2
2014-09-02
Data retention secondary voltage regulator
Grant 8,536,853 - Sessions September 17, 2
2013-09-17
Data retention secondary voltage regulator
Grant 8,362,757 - Sessions January 29, 2
2013-01-29
Data Retention Secondary Voltage Regulator
App 20120326694 - Sessions; D.C.
2012-12-27
High speed rail to rail phase splitter for providing a symmetrical differential output signal having low skew
App 20110050341 - Khoury; Elie G. ;   et al.
2011-03-03
High speed driver equalization
Grant 7,868,804 - Khoury , et al. January 11, 2
2011-01-11
Data Retention Secondary Voltage Regulator
App 20100315056 - Sessions; D.C.
2010-12-16
Current-time digital-to-analog converter
Grant 7,764,213 - Bartling , et al. July 27, 2
2010-07-27
High speed differential receiver with rail to rail common mode operation having a symmetrical differential output signal with low skew
Grant 7,724,087 - Khoury , et al. May 25, 2
2010-05-25
Dynamic State Configuration Restore
App 20100121988 - Lahti; Gregg ;   et al.
2010-05-13
Current-Time Digital-to-Analog Converter
App 20100001889 - Bartling; James E. ;   et al.
2010-01-07
High Speed Driver Equalization
App 20090179682 - Khoury; Elie ;   et al.
2009-07-16
High Speed Differential Receiver with Rail to Rail Common Mode Operation Having a Symmetrical Differential Output Signal with Low Skew
App 20080258812 - Khoury; Elie G. ;   et al.
2008-10-23
Parallel data communication realignment of data sent in multiple groups
Grant 7,085,950 - Ehmann , et al. August 1, 2
2006-08-01
Intelligent speaker training using microphone feedback and pre-loaded templates
Grant 6,766,025 - Levy , et al. July 20, 2
2004-07-20
Parallel communication based on balanced data-bit encoding
Grant 6,636,166 - Sessions , et al. October 21, 2
2003-10-21
Real-time channel calibration method and arrangement
Grant 6,606,576 - Sessions August 12, 2
2003-08-12
Parallel communication based on balanced data-bit encoding
App 20030088317 - Sessions, D.C. ;   et al.
2003-05-08
Parallel data communication realignment of data sent in multiple groups
App 20030065987 - Ehmann, Gregory E. ;   et al.
2003-04-03
Substrate Noise Isolation Using Selective Buried Diffusions
App 20020184558 - Sessions, D.C.
2002-12-05
Parallel data communication consuming low power
App 20020184544 - Svestka, Ivan ;   et al.
2002-12-05
Real-time channel calibration method and arrangement
App 20020138224 - Sessions, D.C.
2002-09-26
System bus with a variable width selectivity configurable at initialization
Grant 6,434,654 - Story , et al. August 13, 2
2002-08-13
Line impedance calibration using actual impedance determination
App 20020067168 - Sessions, D.C.
2002-06-06
5-ary receiver utilizing common mode insensitive differential offset comparator
Grant 6,348,882 - Ciccone , et al. February 19, 2
2002-02-19
CMOS high-to-low voltage buffer
Grant 6,166,580 - Sessions December 26, 2
2000-12-26
High-speed logic embodied differential dynamic CMOS true single phase clock latches and flip-flops with single transistor clock latches
Grant 6,069,495 - Ciccone , et al. May 30, 2
2000-05-30
Pseudo-differential logic receiver
Grant 5,994,925 - Sessions November 30, 1
1999-11-30
Output driver with constant source impedance
Grant 5,933,041 - Sessions , et al. August 3, 1
1999-08-03
Arrangement for selective generation of an output signal related to a clock signal and method therefor
Grant 5,828,249 - Sessions October 27, 1
1998-10-27

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