Seshadri; Indira

Patent Applications and Registrations

Patent applications and USPTO patent grants for Seshadri; Indira.The latest application filed is for "sacrificial fin for contact self-alignment".

Company Profile

58.37.44

Seshadri; Indira - Niskayuna US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Sacrificial Fin For Contact Self-alignment App 20220262923 - Mignot; Yann ; et al.	2022-08-18
Vertical Field Effect Transistor With Crosslink Fin Arrangement App 20220199776 - Seshadri; Indira ; et al.	2022-06-23
Staggered Stacked Vertical Crystalline Semiconducting Channels App 20220149042 - Kang; Tsung-Sheng ; et al.	2022-05-12
Sacrificial fin for contact self-alignment Grant 11,316,029 - Mignot , et al. April 26, 2	2022-04-26
Bottom Source/drain Etch With Fin-cut-last-vtfet App 20220069106 - Li; Tao ; et al.	2022-03-03
Staggered stacked vertical crystalline semiconducting channels Grant 11,251,182 - Kang , et al. February 15, 2	2022-02-15
Bottom source/drain etch with fin-cut-last-VTFET Grant 11,245,027 - Li , et al. February 8, 2	2022-02-08
Self-priming resist for generic inorganic hardmasks Grant 11,226,561 - Liu , et al. January 18, 2	2022-01-18
Metal Cut Patterning And Etching To Minimize Interlayer Dielectric Layer Loss App 20220005698 - Chung; Kisup ; et al.	2022-01-06
Sacrificial Fin For Contact Self-alignment App 20210328041 - Mignot; Yann ; et al.	2021-10-21
Metal cut patterning and etching to minimize interlayer dielectric layer loss Grant 11,133,189 - Chung , et al. September 28, 2	2021-09-28
Vertically Stacked Fin Semiconductor Devices App 20210296438 - Joseph; Praveen ; et al.	2021-09-23
Staggered Stacked Vertical Crystalline Semiconducting Channels App 20210296314 - Kang; Tsung-Sheng ; et al.	2021-09-23
Bottom Source/drain Etch With Fin-cut-last-vtfet App 20210288164 - Li; Tao ; et al.	2021-09-16
Tunable hardmask for overlayer metrology contrast Grant 11,121,024 - De Silva , et al. September 14, 2	2021-09-14
Vertically stacked fin semiconductor devices Grant 11,075,266 - Joseph , et al. July 27, 2	2021-07-27
Semiconductor device with multiple threshold voltages Grant 11,075,081 - Joseph , et al. July 27, 2	2021-07-27
Transistor Structure With N/p Boundary Buffer App 20210118743 - Lallement; Romain ; et al.	2021-04-22
Fin cut profile using fin base liner Grant 10,985,025 - Miller , et al. April 20, 2	2021-04-20
Transistor structure with n/p boundary buffer Grant 10,903,124 - Lallement , et al. January 26, 2	2021-01-26
Techniques to improve critical dimension width and depth uniformity between features with different layout densities Grant 10,832,945 - Saulnier , et al. November 10, 2	2020-11-10
Transistor Structure With N/p Boundary Buffer App 20200350212 - Lallement; Romain ; et al.	2020-11-05
Vertically Stacked Fin Semiconductor Devices App 20200343338 - Joseph; Praveen ; et al.	2020-10-29
Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions Grant 10,818,751 - Ebrish , et al. October 27, 2	2020-10-27
High temperature ultra-fast annealed soft mask for semiconductor devices Grant 10,804,106 - Ebrish , et al. October 13, 2	2020-10-13
Nanosheet Transistor Barrier For Electrically Isolating The Substrate From The Source Or Drain Regions App 20200279913 - Ebrish; Mona A. ; et al.	2020-09-03
Enabling Residue Free Gap Fill Between Nanosheets App 20200279956 - SESHADRI; Indira ; et al.	2020-09-03
Techniques to Improve Critical Dimension Width and Depth Uniformity Between Features with Different Layout Densities App 20200266100 - Saulnier; Nicole ; et al.	2020-08-20
Boundary protection for CMOS multi-threshold voltage devices Grant 10,741,454 - Guo , et al. A	2020-08-11
Controlling fin hardmask cut profile using a sacrificial epitaxial structure Grant 10,741,452 - Miller , et al. A	2020-08-11
Metal cut patterning and etching to minimize interlayer dielectric layer loss Grant 10,734,234 - Chung , et al.	2020-08-04
Nanosheet substrate to source/drain isolation Grant 10,734,523 - Lie , et al.	2020-08-04
Damage free hardmask strip Grant 10,699,912 - Seshadri , et al.	2020-06-30
Surface treatment of titanium containing hardmasks Grant 10,678,135 - De Silva , et al.	2020-06-09
Controlling gate length of vertical transistors Grant 10,665,715 - Joseph , et al.	2020-05-26
Semiconductor device with multiple threshold voltages Grant 10,665,461 - Joseph , et al.	2020-05-26
Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer Grant 10,656,527 - De Silva , et al.	2020-05-19
Enabling residue free gap fill between nanosheets Grant 10,658,521 - Seshadri , et al.	2020-05-19
Controlling Fin Hardmask Cut Profile Using A Sacrificial Epitaxial Structure App 20200135570 - Miller; Eric R. ; et al.	2020-04-30
Fin Cut Profile Using Fin Base Liner App 20200135484 - Miller; Eric R. ; et al.	2020-04-30
Approach to prevent collapse of high aspect ratio Fin structures for vertical transport Fin field effect transistor devices Grant 10,629,489 - Seshadri , et al.	2020-04-21
Low undercut N-P work function metal patterning in nanosheet replacement metal gate process Grant 10,629,495 - Seshadri , et al.	2020-04-21
Damage Free Hardmask Strip App 20200118831 - Seshadri; Indira ; et al.	2020-04-16
Dielectric gap fill evaluation for integrated circuits Grant 10,622,250 - Chu , et al.	2020-04-14
Tunable hardmask for overlayer metrology contrast Grant 10,622,248 - De Silva , et al.	2020-04-14
Surface Treatment Of Titanium Containing Hardmasks App 20200105520 - De Silva; Ekmini A. ; et al.	2020-04-02
Semiconductor Device With Multiple Threshold Voltages App 20200098569 - Joseph; Praveen ; et al.	2020-03-26
Approach To Prevent Collapse Of High Aspect Ratio Fin Structures For Vertical Transport Fin Field Effect Transistor Devices App 20200098639 - Seshadri; Indira ; et al.	2020-03-26
Semiconductor Device With Multiple Threshold Voltages App 20200098570 - Joseph; Praveen ; et al.	2020-03-26
Wet strippable OPL using reversible UV crosslinking and de-crosslinking Grant 10,586,697 - De Silva , et al.	2020-03-10
Controlling Gate Length Of Vertical Transistors App 20200075761 - Joseph; Praveen ; et al.	2020-03-05
Boundary Protection For Cmos Multi-threshold Voltage Devices App 20200051872 - Guo; Jing ; et al.	2020-02-13
Nanosheet Substrate To Source/drain Isolation App 20200052107 - Lie; Fee Li ; et al.	2020-02-13
Patterning Material Film Stack With Hard Mask Layer Configured To Support Selective Deposition On Patterned Resist Layer App 20200050113 - De Silva; Ekmini Anuja ; et al.	2020-02-13
Self-priming Resist For Generic Inorganic Hardmasks App 20200050108 - Liu; Chi-Chun ; et al.	2020-02-13
Tunable Hardmask For Overlayer Metrology Contrast App 20190371651 - De Silva; Ekmini A. ; et al.	2019-12-05
Inverse Tone Direct Print Euv Lithography Enabled By Selective Material Deposition App 20190355625 - JOSEPH; Praveen ; et al.	2019-11-21
Enabling Residue Free Gap Fill Between Nanosheets App 20190355851 - SESHADRI; Indira ; et al.	2019-11-21
Wet Strippable Opl Using Reversible Uv Crosslinking And De-crosslinking App 20190295841 - De Silva; Ekmini A. ; et al.	2019-09-26
Patterning material film stack comprising hard mask layer having high metal content interface to resist layer Grant 10,395,925 - De Silva , et al. A	2019-08-27
High Temperature Ultra-fast Annealed Soft Mask For Semiconductor Devices App 20190259616 - Ebrish; Mona ; et al.	2019-08-22
Wet strippable OPL using reversible UV crosslinking and de-crosslinking Grant 10,388,510 - De Silva , et al. A	2019-08-20
Vertical transport FET with two or more gate lengths Grant 10,361,127 - Karve , et al.	2019-07-23
Self-aligned double patterning formed fincut Grant 10,361,129 - Sieg , et al.	2019-07-23
Wet Strippable Opl Using Reversible Uv Crosslinking And De-crosslinking App 20190221423 - De Silva; Ekmini A. ; et al.	2019-07-18
Simplified block patterning with wet strippable hardmask for high-energy implantation Grant 10,354,922 - De Silva , et al. July 16, 2	2019-07-16
Low Undercut N-p Work Function Metal Patterning In Nanosheet Replacement Metal Gate Process App 20190214311 - Seshadri; Indira ; et al.	2019-07-11
Patterning Material Film Stack Comprising Hard Mask Layer Having High Metal Content Interface To Resist Layer App 20190206681 - De Silva; Ekmini Anuja ; et al.	2019-07-04
Tunable Hardmask For Overlayer Metrology Contrast App 20190206722 - De Silva; Ekmini A. ; et al.	2019-07-04
Vertical Transport Fet With Two Or More Gate Lengths App 20190206738 - Karve; Gauri ; et al.	2019-07-04
Simplified Block Patterning With Wet Strippable Hardmask For High-energy Implantation App 20190198398 - De Silva; Ekmini Anuja ; et al.	2019-06-27
Metal Cut Patterning And Etching To Minimize Interlayer Dielectric Layer Loss App 20190198327 - Chung; Kisup ; et al.	2019-06-27
Patterning Material Film Stack With Hard Mask Layer Configured To Support Selective Deposition On Patterned Resist Layer App 20190196340 - De Silva; Ekmini Anuja ; et al.	2019-06-27
Dielectric Gap Fill Evaluation For Integrated Circuits App 20190189503 - Chu; Isabel Cristina ; et al.	2019-06-20
Metal Cut Patterning And Etching To Minimize Interlayer Dielectric Layer Loss App 20190189452 - Chung; Kisup ; et al.	2019-06-20
Dielectric Gap Fill Evaluation For Integrated Circuits App 20190189504 - Chu; Isabel Cristina ; et al.	2019-06-20
Surface Treatment Of Titanium Containing Hardmasks App 20190189429 - De Silva; Ekmini A. ; et al.	2019-06-20
Dielectric gap fill evaluation for integrated circuits Grant 10,312,140 - Chu , et al.	2019-06-04
Inverse tone direct print EUV lithography enabled by selective material deposition Grant 10,304,744 - Joseph , et al.	2019-05-28
Low undercut N-P work function metal patterning in nanosheet replacement metal gate process Grant 10,276,452 - Seshadri , et al.	2019-04-30
Direct gate patterning for vertical transport field effect transistor Grant 10,176,997 - De Silva , et al. J	2019-01-08

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.