Sesha Sai Aduru; Venkata Raghava
Patent Applications and Registrations
Patent applications and USPTO patent grants for Sesha Sai Aduru; Venkata Raghava.The latest application filed is for "multi-level clock gate controls to address scan mode power droop and voltage bump requirement".
- Sesha Sai Aduru; Venkata Raghava - Bangalore IN
| Patent | Date |
|---|---|
| Multi-level Clock Gate Controls To Address Scan Mode Power Droop And Voltage Bump Requirement App 20180019733 - Tiwari; Rajesh ; et al. | 2018-01-18 |
| Dynamically Configurable Shared Scan Clock Channel Architecture App 20170184665 - Tiwari; Rajesh ; et al. | 2017-06-29 |
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