loadpatents
name:-0.0091168880462646
name:-0.008368968963623
name:-0.0043950080871582
Sendig; Friedrich Gunter Kurt Patent Filings

Sendig; Friedrich Gunter Kurt

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sendig; Friedrich Gunter Kurt.The latest application filed is for "creating and reusing customizable structured interconnects".

Company Profile
4.7.7
  • Sendig; Friedrich Gunter Kurt - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Creating and reusing customizable structured interconnects
Grant 10,909,300 - Lin , et al. February 2, 2
2021-02-02
Creating and Reusing Customizable Structured Interconnects
App 20200089835 - Lin; Hsiang-Wen Jimmy ;   et al.
2020-03-19
Creating and reusing customizable structured interconnects
Grant 10,528,696 - Lin , et al. J
2020-01-07
Reuse of extracted layout-dependent effects for circuit design using circuit stencils
Grant 10,521,535 - Oriordan , et al. Dec
2019-12-31
Integrated circuit design using generation and instantiation of circuit stencils
Grant 10,380,297 - Sendig , et al. A
2019-08-13
Placement of circuit elements in regions with customized placement grids
Grant 10,275,560 - Basaran , et al.
2019-04-30
Reuse of extracted layout-dependent effects for circuit design using circuit stencils
Grant 10,102,324 - Oriordan , et al. October 16, 2
2018-10-16
Integrated circuit design using generation and instantiation of circuit stencils
Grant 10,078,715 - Sendig , et al. September 18, 2
2018-09-18
Integrated Circuit Design Using Generation And Instantiation Of Circuit Stencils
App 20180089340 - Sendig; Friedrich Gunter Kurt ;   et al.
2018-03-29
Reuse Of Extracted Layout-dependent Effects For Circuit Design Using Circuit Stencils
App 20180068036 - Oriordan; Donald John ;   et al.
2018-03-08
Placement Of Circuit Elements In Regions With Customized Placement Grids
App 20170344689 - Basaran; Bulent ;   et al.
2017-11-30
Integrated Circuit Design Using Generation and Instantiation of Circuit Stencils
App 20170249416 - Sendig; Friedrich Gunter Kurt ;   et al.
2017-08-31
Reuse Of Extracted Layout-dependent Effects For Circuit Design Using Circuit Stencils
App 20170249400 - Oriordan; Donald John ;   et al.
2017-08-31
Creating and Reusing Customizable Structured Interconnects
App 20170249414 - Lin; Hsiang-Wen Jimmy ;   et al.
2017-08-31

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed