| Patent | Date |
|---|
System And Method For Modeling Memory Devices With Latency
App 20220066801 - Selvidge; Charles W. ; et al. | 2022-03-03 |
Reduce/broadcast computation-enabled switching elements in an emulation network
Grant 11,113,441 - Selvidge , et al. September 7, 2 | 2021-09-07 |
Bandwidth test in networking System-on-Chip verification
Grant 10,664,566 - Krishnamurthy , et al. | 2020-05-26 |
Concurrent testbench and software driven verification
Grant 10,664,563 - Bhattacharya , et al. | 2020-05-26 |
Latency test in networking system-on-chip verification
Grant 10,657,217 - Krishnamurthy , et al. | 2020-05-19 |
Selective conditional stall for hardware-based circuit design verification
Grant 10,579,776 - Selvidge , et al. | 2020-03-03 |
Target capture and replay in emulation
Grant 10,503,848 - Suresh , et al. Dec | 2019-12-10 |
Content addressable memory modeling in emulation and prototyping
Grant 10,410,713 - Selvidge , et al. Sept | 2019-09-10 |
Concurrent Testbench and Software Driven Verification
App 20180285484 - Bhattacharya; Debdutta ; et al. | 2018-10-04 |
Bandwidth Test In Networking System-On-Chip Verification
App 20180113961 - Suresh; Krishnamurthy ; et al. | 2018-04-26 |
Latency Test In Networking System-On-Chip Verification
App 20180113970 - Suresh; Krishnamurthy ; et al. | 2018-04-26 |
Modeling memory in emulation based on cache
Grant 9,898,563 - Suresh , et al. February 20, 2 | 2018-02-20 |
Debug Environment For A Multi User Hardware Assisted Verification System
App 20180032357 - Suresh; Krishnamurthy ; et al. | 2018-02-01 |
Data Injection In Emulation Without Rebooting
App 20180011956 - Kumar; Ajay ; et al. | 2018-01-11 |
Target Capture And Replay In Emulation
App 20170337309 - Suresh; Krishnamurthy ; et al. | 2017-11-23 |
Target capture and replay in emulation
Grant 9,767,237 - Suresh , et al. September 19, 2 | 2017-09-19 |
Debug environment for a multi user hardware assisted verification system
Grant 9,703,579 - Suresh , et al. July 11, 2 | 2017-07-11 |
Target Capture And Replay In Emulation
App 20170140082 - Suresh; Krishnamurthy ; et al. | 2017-05-18 |
Modeling Memory In Emulation Based On Cache
App 20170140083 - Suresh; Krishnamurthy ; et al. | 2017-05-18 |
Third party component debugging for integrated circuit design
Grant 9,619,600 - Selvidge , et al. April 11, 2 | 2017-04-11 |
Switching activity reduction through retiming
Grant 9,305,126 - Selvidge , et al. April 5, 2 | 2016-04-05 |
Adaptive clock management in emulation
Grant 9,165,099 - Suresh , et al. October 20, 2 | 2015-10-20 |
Switching Activity Reduction Through Retiming
App 20150269295 - Selvidge; Charles W. ; et al. | 2015-09-24 |
Third Party Component Debugging For Integrated Circuit Design
App 20150149973 - Selvidge; Charles W. ; et al. | 2015-05-28 |
Adaptive Clock Management In Emulation
App 20150100931 - Suresh; Krishnamurthy ; et al. | 2015-04-09 |
Third party component debugging for integrated circuit design
Grant 8,843,861 - Selvidge September 23, 2 | 2014-09-23 |
Partitionless Multi User Support For Hardware Assisted Verification
App 20140052430 - Suresh; Krishnamurthy ; et al. | 2014-02-20 |
Partitionless Multi User Support For Hardware Assisted Verification
App 20140032204 - Suresh; Krishnamurthy ; et al. | 2014-01-30 |
Register transfer level design compilation advisor
Grant 8,516,411 - Gupta , et al. August 20, 2 | 2013-08-20 |
Register Transfer Level Design Compilation Advisor
App 20120180011 - Gupta; Sanjay ; et al. | 2012-07-12 |
Acyclic modeling of combinational loops
Grant 8,181,129 - Gupta , et al. May 15, 2 | 2012-05-15 |
Acyclic Modeling of Combinational Loops
App 20090044157 - Gupta; Amit ; et al. | 2009-02-12 |
Software state replay
Grant 7,480,610 - Scott , et al. January 20, 2 | 2009-01-20 |
Acyclic modeling of combinational loops
Grant 7,454,722 - Gupta , et al. November 18, 2 | 2008-11-18 |
Functional verification of logic and memory circuits with multiple asynchronous domains
Grant 7,143,377 - Kudlugi , et al. November 28, 2 | 2006-11-28 |
Acyclic modeling of combinational loops
App 20060123300 - Gupta; Amit ; et al. | 2006-06-08 |
Software state replay
App 20060074622 - Scott; David C. ; et al. | 2006-04-06 |
Non-synchronized multiplex data transport across synchronous systems
Grant 6,961,691 - Selvidge , et al. November 1, 2 | 2005-11-01 |
Functional verification of logic and memory circuits with multiple asynchronous domains
Grant 6,817,001 - Kudlugi , et al. November 9, 2 | 2004-11-09 |
Logic analysis system for logic emulation systems
App 20010010036 - Stewart, Kem ; et al. | 2001-07-26 |
Logic analysis system for logic emulation systems
Grant 6,223,148 - Stewart , et al. April 24, 2 | 2001-04-24 |
Formulation and method of preparation of energy fortified diesel fuel
Grant 6,039,771 - Selvidge , et al. March 21, 2 | 2000-03-21 |
Transition analysis and circuit resynthesis method and device for digital circuit modeling
Grant 6,009,531 - Selvidge , et al. December 28, 1 | 1999-12-28 |
Pipe lined static router and scheduler for configurable logic system performing simultaneous communications and computation
Grant 5,850,537 - Selvidge , et al. December 15, 1 | 1998-12-15 |
Programmable multiplexing input/output port
Grant 5,847,578 - Noakes , et al. December 8, 1 | 1998-12-08 |
Logic analysis system for logic emulation systems
Grant 5,802,348 - Stewart , et al. September 1, 1 | 1998-09-01 |
Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation
Grant 5,659,716 - Selvidge , et al. August 19, 1 | 1997-08-19 |
Transition analysis and circuit resynthesis method and device for digital circuit modeling
Grant 5,649,176 - Selvidge , et al. July 15, 1 | 1997-07-15 |
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