Seliger, Frank

USPTO Trademark & Patent Filings

Trademark applications and grants for Seliger, Frank. Seliger, Frank has 4 trademark applications. The latest application filed is for "a symbol or image mark"

Company Profile

Frank Seliger
Seliger, Frank
frank seliger
SELIGER; Frank - Dresden DE
Seliger; Frank - Dresden DE
SELIGER; FRANK - Altdorf DE

Entity Type	INDIVIDUAL
Address	209 West Powell Lane 201 West Powell Lane Austin, TEXAS UNITED STATES 78753

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks Patents

Patent Applications

Patent Application	Date
ENHANCING INTEGRITY OF A HIGH-K GATE STACK BY PROTECTING A LINER AT THE GATE BOTTOM DURING GATE HEAD EXPOSURE 20130157432 - 13/672800 BEYER; Sven ; et al.	2013-06-20
Sophisticated Gate Electrode Structures Formed by Cap Layer Removal with Reduced Loss of Embedded Strain-Inducing Semiconductor Material 20120196417 - 13/358101 Kronholz; Stephan ; et al.	2012-08-02
INFORMATION PROCESSING APPARATUS, A SERVER APPARATUS, A METHOD OF AN INFORMATION PROCESSING APPARATUS, A METHOD OF A SERVER APPARATUS, AND AN APPARATUS EXECUTABLE PROGRAM 20120185694 - 13/432715 MUNETOH; SEIJI ; et al.	2012-07-19
CAP REMOVAL IN A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL FILL MATERIAL 20110129980 - 12/905655 Heinrich; Jens ; et al.	2011-06-02
CORNER ROUNDING IN A REPLACEMENT GATE APPROACH BASED ON A SACRIFICIAL FILL MATERIAL APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION 20110104880 - 12/894985 Heinrich; Jens ; et al.	2011-05-05
Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device 8,987,103 - 12/776,674 Lenski , et al. March 24, 2	2015-03-24
Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device 8,987,103 - 12/776,674 Lenski , et al. March 24, 2	2015-03-24
Enhancing integrity of a high-K gate stack by protecting a liner at the gate bottom during gate head exposure 8,932,930 - 13/672,800 Beyer , et al. January 13, 2	2015-01-13
Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions 8,765,542 - 13/765,797 Patzer , et al. July 1, 2	2014-07-01
Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material 8,765,559 - 13/358,101 Kronholz , et al. July 1, 2	2014-07-01

Patent Grants & Applications

Trademark Applications

Mark Image Registration \| Serial	Trademark Application Date
"Symbol/Image" 98166820	Symbol/Image 2023-09-06
"NO GO RINO ??" 98166641	NO GO RINO ?? 2023-09-06
"Symbol/Image" 88507422	Symbol/Image 2019-07-10
"O.O.P.S. ODD ORIGINAL PROTECTIVE SUNSCREENS INC." 74589185	O.O.P.S. ODD ORIGINAL PROTECTIVE SUNSCREENS INC. 1994-10-21

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