Sei; Toshikazu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sei; Toshikazu.The latest application filed is for "semiconductor integrated circuit with a logic circuit including a data holding circuit".

Company Profile

0.20.12

Sei; Toshikazu - Kawasaki JP
Sei; Toshikazu - Kawasaki-shi JP
Sei; Toshikazu - Tokyo JP
Sei; Toshikazu - Kanagawa-ken JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor integrated circuit with a logic circuit including a data holding circuit Grant 7,759,995 - Ishii , et al. July 20, 2	2010-07-20
Semiconductor Integrated Circuit with a Logic Circuit Including a Data Holding Circuit App 20090039937 - Ishii; Chihiro ; et al.	2009-02-12
Semiconductor integrated circuit with a logic circuit including a data holding circuit Grant 7,446,581 - Ishii , et al. November 4, 2	2008-11-04
Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal Grant 7,444,614 - Maeno , et al. October 28, 2	2008-10-28
Semiconductor integrated circuit with mixed gate array and standard cell Grant RE39,469 - Fudanuki , et al. January 16, 2	2007-01-16
Semiconductor integrated circuit device having an ESD protection unit Grant 7,123,054 - Satou , et al. October 17, 2	2006-10-17
Semiconductor integrated circuit device advantageous for microfabrication and manufacturing method for the same App 20060199325 - Maeno; Muneaki ; et al.	2006-09-07
Semiconductor integrated circuit with a logic circuit including a data holding circuit App 20060082404 - Ishii; Chihiro ; et al.	2006-04-20
Semiconductor device, designing method thereof, and recording medium storing semicondcutor designing program App 20060012050 - Maeno; Muneaki ; et al.	2006-01-19
Semiconductor integrated circuit device and wiring arranging method thereof Grant 6,962,868 - Sakamoto , et al. November 8, 2	2005-11-08
Semiconductor integrated circuit device with I/O cell and connection member Grant 6,919,632 - Sei July 19, 2	2005-07-19
Semiconductor device provided using wiring data of common design core Grant 6,915,498 - Hashiba , et al. July 5, 2	2005-07-05
Semiconductor integrated circuit making use of standard cells Grant 6,885,071 - Umemoto , et al. April 26, 2	2005-04-26
Semiconductor integrated circuit device having an ESD protection unit App 20050047042 - Satou, Youichi ; et al.	2005-03-03
Semiconductor integrated circuit device and wiring arranging method thereof Grant 6,844,630 - Sakamoto , et al. January 18, 2	2005-01-18
Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program Grant 6,826,742 - Maeno , et al. November 30, 2	2004-11-30
Semiconductor integrated circuit device and wiring arranging method thereof App 20040227161 - Sakamoto, Shinsuke ; et al.	2004-11-18
Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program Grant 6,753,611 - Maeno , et al. June 22, 2	2004-06-22
Semiconductor integrated circuit making use of standard cells App 20040079969 - Umemoto, Yasunobu ; et al.	2004-04-29
Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program App 20040065907 - Maeno, Muneaki ; et al.	2004-04-08
Semiconductor integrated circuit making use of standard cells Grant 6,690,073 - Umemoto , et al. February 10, 2	2004-02-10
Semiconductor integrated circuit device with I/O cell and connection member App 20030057549 - Sei, Toshikazu	2003-03-27
Semiconductor device App 20030015773 - Hashiba, Yoshiaki ; et al.	2003-01-23
Semiconductor integrated circuit device and wiring arranging method thereof App 20020117757 - Sakamoto, Shinsuke ; et al.	2002-08-29
Standard cell having a special region and semiconductor integrated circuit containing the standard cells Grant 6,410,972 - Sei , et al. June 25, 2	2002-06-25
Semiconductor integrated circuit making use of standard cells App 20010028069 - Umemoto, Yasunobu ; et al.	2001-10-11
Master slice LSI and layout method for the same Grant 6,271,548 - Umemoto , et al. August 7, 2	2001-08-07
Semiconductor integrated circuit with mixed gate array and standard cell Grant 6,054,872 - Fudanuki , et al. April 25, 2	2000-04-25
Semiconductor integrated circuit with buffer circuit and manufacturing method thereof Grant 5,614,842 - Doke , et al. March 25, 1	1997-03-25
Gate array semiconductor circuit device, input circuit, output circuit and voltage lowering circuit Grant 5,352,942 - Tanaka , et al. October 4, 1	1994-10-04
Bipolar transistor/insulated gate transistor hybrid semiconductor device Grant 5,272,366 - Sei , et al. December 21, 1	1993-12-21
CMOS output buffer with pre-drive circuitry to control slew rate of main drive transistors Grant 5,216,293 - Sei , et al. June 1, 1	1993-06-01

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