Seethamraju; Srisai R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Seethamraju; Srisai R..The latest application filed is for "jitter self-test using timestamps".

Company Profile

1.11.8

Seethamraju; Srisai R. - Nashua NH

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Jitter Self-test Using Timestamps App 20220123877 - Ranganathan; Raghunandan K. ; et al.	2022-04-21
Jitter self-test using timestamps Grant 11,228,403 - Ranganathan , et al. January 18, 2	2022-01-18
Spur and quantization noise cancellation for PLLS with non-linear phase detection Grant 11,038,521 - Rafi , et al. June 15, 2	2021-06-15
Jitter Self-test Using Timestamps App 20210176020 - Ranganathan; Raghunandan K. ; et al.	2021-06-10
Compensating for thermal lag in temperature compensated crystal oscillators Grant 10,404,209 - Cali , et al. Sep	2019-09-03
Compensating for temperature-dependent hysteresis in a temperature compensated crystal oscillator Grant 10,164,643 - Seethamraju , et al. Dec	2018-12-25
Compensating For Temperature-dependent Hysteresis In A Temperature Compensated Crystal Oscillator App 20180076819 - Seethamraju; Srisai R. ; et al.	2018-03-15
Compensating For Thermal Lag In Temperature Compensated Crystal Oscillators App 20180069553 - Cali; Joseph D. ; et al.	2018-03-08
Amplifier topology achieving high DC gain and wide output voltage range Grant 9,444,406 - Perrott , et al. September 13, 2	2016-09-13
Glitchless clock switching that handles stopped clocks Grant 9,207,704 - Anker , et al. December 8, 2	2015-12-08
Glitchless Clock Switching That Handles Stopped Clocks App 20140118033 - Anker; William J. ; et al.	2014-05-01
Digital hold in a phase-locked loop Grant 8,532,243 - Seethamraju , et al. September 10, 2	2013-09-10
Compensation for crystal offset in PLL-based crystal oscillators Grant 8,242,849 - Seethamraju , et al. August 14, 2	2012-08-14
Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics Grant 7,443,250 - Seethamraju , et al. October 28, 2	2008-10-28
Digital Hold In A Phase-locked Loop App 20080191762 - Seethamraju; Srisai R. ; et al.	2008-08-14
Technique for switching between input clocks in a phase-locked loop Grant 7,405,628 - Hulfachor , et al. July 29, 2	2008-07-29
Technique For Switching Between Input Clocks In A Phase-locked Loop App 20080079501 - Hulfachor; Ronald B. ; et al.	2008-04-03
Programmable Phase-locked Loop Responsive To A Selected Bandwidth And A Selected Reference Clock Signal Frequency To Adjust Circuit Characteristics App 20080079510 - Seethamraju; Srisai R. ; et al.	2008-04-03

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