Seeman; Thomas R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Seeman; Thomas R..The latest application filed is for "mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption".

Company Profile

0.12.8

Seeman; Thomas R. - Colorado Springs CO US
Seeman; Thomas R. - Tomball TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Mobile Electronic Devices Utilizing Reconfigurable Processing Techniques To Enable Higher Speed Applications With Lowered Power Consumption App 20130157639 - Huppenthal; Jon M. ; et al.	2013-06-20
Heterogeneous Computing System Comprising A Switch/network Adapter Port Interface Utilizing Load-reduced Dual In-line Memory Modules (lr-dimms) Incorporating Isolation Memory Buffers App 20120117318 - Burton; Lee A. ; et al.	2012-05-10
Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers Grant 7,565,461 - Huppenthal , et al. July 21, 2	2009-07-21
Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format Grant 7,421,524 - Huppenthal , et al. September 2, 2	2008-09-02
Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format Grant 7,373,440 - Huppenthal , et al. May 13, 2	2008-05-13
Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers Grant 7,197,575 - Huppenthal , et al. March 27, 2	2007-03-27
Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port Grant 7,003,593 - Huppenthal , et al. February 21, 2	2006-02-21
Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers App 20050283546 - Huppenthal, Jon M. ; et al.	2005-12-22
Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format App 20050091434 - Huppenthal, Jon M. ; et al.	2005-04-28
Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers App 20050076152 - Huppenthal, Jon M. ; et al.	2005-04-07
Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port App 20030061432 - Huppenthal, Jon M. ; et al.	2003-03-27
Bus-to-bus bridge in computer system, with fast burst memory range Grant RE37,980 - Elkhoury , et al. February 4, 2	2003-02-04
Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format App 20020019926 - Huppenthal, Jon M. ; et al.	2002-02-14
Bus-to-bus bridge in computer system, with fast burst memory range Grant 6,148,359 - Elkhoury , et al. November 14, 2	2000-11-14
Lock protocol for PCI bus using an additional "superlock" signal on the system bus Grant 6,098,134 - Michels , et al. August 1, 2	2000-08-01
Computer system with bridges having posted memory write buffers Grant 6,085,274 - Seeman July 4, 2	2000-07-04
Computer system using posted memory write buffers in a bridge to implement system management mode Grant 5,881,253 - Seeman March 9, 1	1999-03-09
Delayed transaction protocol for computer system bus Grant 5,870,567 - Hausauer , et al. February 9, 1	1999-02-09
Computer system implementing a stop clock acknowledge special cycle Grant 5,832,243 - Seeman November 3, 1	1998-11-03

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