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Patent applications and USPTO patent grants for Seawright; James Andrew Garrard.The latest application filed is for "clock model for formal verification of a digital circuit description".
Patent | Date |
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Clock model for formal verification of a digital circuit description Grant 8,060,847 - Seawright , et al. November 15, 2 | 2011-11-15 |
Clock Model For Formal Verification Of A Digital Circuit Description App 20090144684 - Seawright; James Andrew Garrard ;   et al. | 2009-06-04 |
Clock model for formal verification of a digital circuit description Grant 7,487,483 - Seawright , et al. February 3, 2 | 2009-02-03 |
Selection of initial states for formal verification Grant 7,454,324 - Seawright , et al. November 18, 2 | 2008-11-18 |
Clock model for formal verification of a digital circuit description App 20070271536 - Seawright; James Andrew Garrard ;   et al. | 2007-11-22 |
Method And Apparatus For Optimized Partitioning Of Finite State Machines Synthesized From Hierarchical High-level Descriptions App 20020023256 - SEAWRIGHT, JAMES ANDREW GARRARD | 2002-02-21 |
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