loadpatents
Patent applications and USPTO patent grants for Scott; David Barry.The latest application filed is for "method and system for latch-up prevention".
Patent | Date |
---|---|
Heterologous biosynthesis of nodulisporic acid Grant 11,453,882 - Nicholson , et al. September 27, 2 | 2022-09-27 |
Method And System For Latch-up Prevention App 20210117605 - Lai; Po-Chia ;   et al. | 2021-04-22 |
Method and system for latch-up prevention Grant 10,872,190 - Lai , et al. December 22, 2 | 2020-12-22 |
Heterologous Biosynthesis Of Nodulisporic Acid App 20200299700 - Nicholson; Matthew Joseph ;   et al. | 2020-09-24 |
Tap Cells App 20200019666 - Lai; Po-Chia ;   et al. | 2020-01-16 |
Standard cells having flexible layout architecture/boundaries Grant 8,504,972 - Hou , et al. August 6, 2 | 2013-08-06 |
Method and apparatus for energy harvest from ambient sources Grant 8,432,071 - Huang , et al. April 30, 2 | 2013-04-30 |
Adaptive Content-aware Aging Simulations App 20120123745 - Sheu; Bing Jay ;   et al. | 2012-05-17 |
Method And Apparatus For Energy Harvest From Ambient Sources App 20120032518 - HUANG; Ming-Chieh ;   et al. | 2012-02-09 |
Wide-range Quick Tunable Transistor Model App 20110153055 - Sheu; Bing J. ;   et al. | 2011-06-23 |
Standard Cells Having Flexible Layout Architecture/Boundaries App 20100269081 - Hou; Yung-Chin ;   et al. | 2010-10-21 |
N+ Poly On High-k Dielectric For Semiconductor Devices App 20080272442 - Venugopal; Ramesh ;   et al. | 2008-11-06 |
N+ poly on high-k dielectric for semiconductor devices Grant 7,407,850 - Venugopal , et al. August 5, 2 | 2008-08-05 |
Area efficient implementation of small blocks in an SRAM array Grant 7,236,396 - Houston , et al. June 26, 2 | 2007-06-26 |
Design method and system for optimum performance in integrated circuits that use power management Grant 7,216,310 - Chatterjee , et al. May 8, 2 | 2007-05-08 |
Area efficient implementation of small blocks in an SRAM array App 20070002617 - Houston; Theodore W. ;   et al. | 2007-01-04 |
N+ poly on high-k dielectric for semiconductor devices App 20060223248 - Venugopal; Ramesh ;   et al. | 2006-10-05 |
Design method and system for optimum performance in integrated circuits that use power management App 20050149887 - Chatterjee, Amitava ;   et al. | 2005-07-07 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.