Schwarz; Eric Mark

Patent Applications and Registrations

Patent applications and USPTO patent grants for Schwarz; Eric Mark.The latest application filed is for "hexadecimal floating point multiply and add instruction".

Company Profile

1.13.7

Schwarz; Eric Mark - Gardiner NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Vector pack and unpack instructions Grant 11,442,726 - Schwarz , et al. September 13, 2	2022-09-13
Hexadecimal Floating Point Multiply And Add Instruction App 20220283818 - Schwarz; Eric Mark ; et al.	2022-09-08
Vector Convert Hexadecimal Floating Point To Scaled Decimal Instruction App 20220276867 - Schwarz; Eric Mark ; et al.	2022-09-01
Decimal scale and convert and split to hexadecimal floating point instruction Grant 11,360,769 - Schwarz , et al. June 14, 2	2022-06-14
Instruction dispatch routing Grant 11,327,766 - Schwarz , et al. May 10, 2	2022-05-10
Instruction Dispatch Routing App 20220035636 - Schwarz; Eric Mark ; et al.	2022-02-03
Unique instruction identifier that identifies common instructions across different code releases Grant 10,903,988 - Belmar , et al. January 26, 2	2021-01-26
Prepare For Shorter Precision (round For Reround) Mode In A Decimal Floating-point Instruction App 20210004206 - Schwarz; Eric Mark ; et al.	2021-01-07
Method and apparatus for prefetching branch history information Grant 7,493,480 - Emma , et al. February 17, 2	2009-02-17
Zero detect in partial sums while adding App 20060184603 - Trong; Son Dao ; et al.	2006-08-17
Floating point bypass register to resolve data dependencies in pipelined instruction sequences App 20040143613 - Clemen, Rainer ; et al.	2004-07-22
Two dimensional branch history table prefetching mechanism App 20040015683 - Emma, Philip G. ; et al.	2004-01-22
Computer processor system for executing RXE format floating point instructions Grant 6,085,313 - Check , et al. July 4, 2	2000-07-04
Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation Grant 6,075,937 - Scalzi , et al. June 13, 2	2000-06-13
Floating point binary quad word format multiply instruction unit Grant 6,055,554 - Schwarz April 25, 2	2000-04-25
Preprocessing of stored target routines for emulating incompatible instructions on a target processor Grant 6,009,261 - Scalzi , et al. December 28, 1	1999-12-28
Method and system for executing denormalized numbers Grant 5,903,479 - Schwarz , et al. May 11, 1	1999-05-11
Method and system of rounding for division or square root: eliminating remainder calculation Grant 5,764,555 - McPherson , et al. June 9, 1	1998-06-09
Method and system of rounding for quadratically converging division or square root Grant 5,737,255 - Schwarz April 7, 1	1998-04-07
Method and system of rounding for quadratically converging division or square root Grant 5,729,481 - Schwarz March 17, 1	1998-03-17

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