loadpatents
Patent applications and USPTO patent grants for Schuppe; Vincent Philippe.The latest application filed is for "circuit layout techniques".
Patent | Date |
---|---|
Circuit Layout Techniques App 20210383050 - Shi; Yulin ;   et al. | 2021-12-09 |
Tile-cell interpolation Grant 10,579,775 - Schuppe , et al. | 2020-03-03 |
Tile-cell Interpolation App 20200019669 - Schuppe; Vincent Philippe ;   et al. | 2020-01-16 |
Inverter circuitry Grant 10,403,643 - Chong , et al. Sep | 2019-09-03 |
Inverter Circuitry App 20180323215 - Chong; Yew Keong ;   et al. | 2018-11-08 |
Dynamic Capacitance Balancing App 20170062043 - Schuppe; Vincent Philippe ;   et al. | 2017-03-02 |
Dynamic capacitance balancing Grant 9,570,157 - Schuppe , et al. February 14, 2 | 2017-02-14 |
Controlling A Voltage Level Of An Access Signal To Reduce Access Disturbs In Semiconductor Memories App 20130308407 - Shyanmugam; Amaranth ;   et al. | 2013-11-21 |
Generating ROM bit cell arrays Grant 8,422,262 - Nevers , et al. April 16, 2 | 2013-04-16 |
Generating ROM bit cell arrays App 20110249481 - Nevers; Yannick Marc ;   et al. | 2011-10-13 |
Generating ROM bit cell arrays Grant 7,961,490 - Nevers , et al. June 14, 2 | 2011-06-14 |
Generating ROM bit cell arrays App 20100177544 - Nevers; Yannick Marc ;   et al. | 2010-07-15 |
Memory device and method of operating such a memory device Grant 7,613,053 - van Winkelhoff , et al. November 3, 2 | 2009-11-03 |
Memory device and method of operating such a memory device App 20090135663 - van Winkelhoff; Nicolaas Klarinus Johannes ;   et al. | 2009-05-28 |
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