Schultz; David P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Schultz; David P..The latest application filed is for "programmable device configuration memory system".

Company Profile

10.61.21

Schultz; David P. - Longmont CO
Schultz; David P. - San Jose CA
Schultz; David P. - Grand Prairie TX
Schultz; David P. - Arlington TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Programmable device configuration memory system Grant 11,386,009 - Schultz , et al. July 12, 2	2022-07-12
Tracing status of a programmable device Grant 11,256,520 - Schultz , et al. February 22, 2	2022-02-22
Configuring programmable logic region via programmable network Grant 11,169,822 - Camarota , et al. November 9, 2	2021-11-09
Programmable Device Configuration Memory System App 20210133107 - SCHULTZ; David P. ; et al.	2021-05-06
Retaining memory during partial reconfiguration Grant 10,963,170 - Kumar , et al. March 30, 2	2021-03-30
Tracing Status Of A Programmable Device App 20210081215 - Schultz; David P. ; et al.	2021-03-18
Partial reconfiguration for Network-on-Chip (NoC) Grant 10,893,005 - Schultz , et al. January 12, 2	2021-01-12
Extend routing range for partial reconfiguration Grant 10,824,786 - Liu , et al. November 3, 2	2020-11-03
Configuring Programmable Logic Region Via Programmable Network App 20200264901 - Camarota; Rafael C. ; et al.	2020-08-20
Retaining Memory During Partial Reconfiguration App 20200241770 - Kumar; Subodh ; et al.	2020-07-30
Circuit for and method of configuring and partially reconfiguring function blocks of an integrated circuit device Grant 10,680,615 - Schultz , et al.	2020-06-09
Peripheral interconnect for configurable slave endpoint circuits Grant 10,621,129 - Swarbrick , et al.	2020-04-14
Partial Reconfiguration For Network-on-chip (noc) App 20200092230 - Schultz; David P. ; et al.	2020-03-19
Circuit and method for ensuring a stable IO interface during partial reconfiguration of a reprogrammable integrated circuit device Grant 10,541,686 - Schultz , et al. Ja	2020-01-21
Multi-chip structure having configurable network-on-chip Grant 10,505,548 - Swarbrick , et al. Dec	2019-12-10
Multi-chip Structure Having Configurable Network-on-chip App 20190363717 - Swarbrick; Ian A. ; et al.	2019-11-28
Peripheral Interconnect For Configurable Slave Endpont Circuits App 20190303323 - Swarbrick; Ian A. ; et al.	2019-10-03
Run length compression and decompression using an alternative value for single occurrences of a run value Grant 10,305,511 - Schultz , et al.	2019-05-28
Circuit arrangement for and a method of enabling a partial reconfiguration of a circuit implemented in an integrated circuit device Grant 9,722,613 - Schultz , et al. August 1, 2	2017-08-01
System and method of actuating a swashplate for main rotor control Grant 9,156,547 - Dickman , et al. October 13, 2	2015-10-13
System and Method of Actuating a Swashplate for Main Rotor Control App 20130209252 - Dickman; Corey J. ; et al.	2013-08-15
Input/output bank architecture for an integrated circuit Grant 8,358,553 - Schultz , et al. January 22, 2	2013-01-22
Error checking parity and syndrome of a block of data with relocated parity bits Grant 8,301,988 - Cory , et al. October 30, 2	2012-10-30
Error checking parity and syndrome of a block of data with relocated parity bits Grant 8,245,102 - Cory , et al. August 14, 2	2012-08-14
Method and apparatus for implementing a cyclic redundancy check circuit Grant 8,225,187 - Schultz , et al. July 17, 2	2012-07-17
Method of and circuit for generating a random number using a multiplier oscillation Grant 8,099,449 - Schultz January 17, 2	2012-01-17
Input/output Bank Architecture For An Integrated Circuit App 20110299351 - Schultz; David P. ; et al.	2011-12-08
Error checking parity and syndrome of a block of data with relocated parity bits Grant 7,895,509 - Cory , et al. February 22, 2	2011-02-22
Digital signal processing element having an arithmetic logic unit Grant 7,882,165 - Simkins , et al. February 1, 2	2011-02-01
Arithmetic logic unit circuit Grant 7,840,630 - Wong , et al. November 23, 2	2010-11-23
Method of selectively programming integrated circuits to compensate for process variations and/or mask revisions Grant 7,529,993 - Schultz May 5, 2	2009-05-05
Error correction for multiple word read Grant 7,430,703 - Schultz September 30, 2	2008-09-30
Error checking parity and syndrome of a block of data with relocated parity bits Grant 7,426,678 - Cory , et al. September 16, 2	2008-09-16
Programmable gate array and embedded circuitry initialization and processing Grant 7,420,392 - Schultz , et al. September 2, 2	2008-09-02
Programmable integrated circuit with selective programming to compensate for process variations and/or mask revisions Grant 7,368,940 - Schultz May 6, 2	2008-05-06
Method and system for configuring an integrated circuit Grant 7,314,174 - Vadi , et al. January 1, 2	2008-01-01
Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability Grant 7,286,382 - Vadi , et al. October 23, 2	2007-10-23
Data monitoring for single event upset in a programmable logic device Grant 7,283,409 - Voogel , et al. October 16, 2	2007-10-16
Reconfiguration port for dynamic reconfiguration-system monitor interface Grant 7,233,532 - Vadi , et al. June 19, 2	2007-06-19
Reconfiguration port for dynamic reconfiguration Grant 7,218,137 - Vadi , et al. May 15, 2	2007-05-15
Method and apparatus for a multiplexed address line driver Grant 7,196,940 - Vadi , et al. March 27, 2	2007-03-27
Two-stage pressure relief valve Grant 7,165,950 - Fenny , et al. January 23, 2	2007-01-23
Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability Grant 7,142,442 - Vadi , et al. November 28, 2	2006-11-28
Reconfiguration port for dynamic reconfiguration--sub-frame access for reconfiguration Grant 7,126,372 - Vadi , et al. October 24, 2	2006-10-24
Data monitoring for single event upset in a programmable logic device Grant 7,109,746 - Voogel , et al. September 19, 2	2006-09-19
Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC) Grant 7,111,217 - Schultz September 19, 2	2006-09-19
Reconfiguration port for dynamic reconfiguration-controller Grant 7,109,750 - Vadi , et al. September 19, 2	2006-09-19
Arithmetic logic unit circuit App 20060206557 - Wong; Anna Wing Wah ; et al.	2006-09-14
Boundary-scan circuit used for analog and digital testing of an integrated circuit Grant 7,102,555 - Collins , et al. September 5, 2	2006-09-05
Digital signal processing element having an arithmetic logic unit App 20060190516 - Simkins; James M. ; et al.	2006-08-24
Integrated three function valve Grant 7,003,949 - Fenny , et al. February 28, 2	2006-02-28
Reconfiguration port for dynamic reconfiguration App 20050248364 - Vadi, Vasisht Mantra ; et al.	2005-11-10
Reconfiguration port for dynamic reconfiguration-controller App 20050242835 - Vadi, Vasisht Mantra ; et al.	2005-11-03
Reconfiguration port for dynamic reconfiguration-system monitor interface App 20050246520 - Vadi, Vasisht Mantra ; et al.	2005-11-03
Boundary-scan Circuit Used For Analog An Ddigital Testing Of An Integrated Circuit App 20050242980 - Collins, Anthony J. ; et al.	2005-11-03
Reconfiguration port for dynamic reconfiguration - sub-frame access for reconfiguration App 20050242834 - Vadi, Vasisht Mantra ; et al.	2005-11-03
Two-stage pressure relief valve App 20050129531 - Fenny, Carlos A. ; et al.	2005-06-16
Programmable gate array and embedded circuitry initialization and processing App 20050040850 - Schultz, David P. ; et al.	2005-02-24
FPGA and embedded circuitry initialization and processing Grant 6,781,407 - Schultz August 24, 2	2004-08-24
Hydraulic hose pair grommet Grant D494,450 - Schultz , et al. August 17, 2	2004-08-17
FPGA and embedded circuitry initialization and processing App 20030128050 - Schultz, David P.	2003-07-10
Programmable logic device capable of preserving state data during partial or complete reconfiguration Grant 6,525,562 - Schultz , et al. February 25, 2	2003-02-25
Digitally controlled impedance for I/O of an integrated circuit device Grant 6,489,837 - Schultz , et al. December 3, 2	2002-12-03
Digitally controlled impedance for I/O of an integrated circuit device Grant 6,445,245 - Schultz , et al. September 3, 2	2002-09-03
Configuration bus interface circuit for FPGAs Grant 6,429,682 - Schultz , et al. August 6, 2	2002-08-06
Digitally controlled impedance for I/O of an integrated circuit device App 20020101278 - Schultz, David P. ; et al.	2002-08-01
Circuit for producing low-voltage differential signals Grant 6,366,128 - Ghia , et al. April 2, 2	2002-04-02
Circuit for converting a logic signal on an output node to a pair of low-voltage differential signals Grant 6,353,334 - Schultz , et al. March 5, 2	2002-03-05
Configuration bus interface circuit for FPGAS Grant 6,262,596 - Schultz , et al. July 17, 2	2001-07-17
Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA Grant 6,255,848 - Schultz , et al. July 3, 2	2001-07-03
Method and structure for configuring FPGAS Grant 6,204,687 - Schultz , et al. March 20, 2	2001-03-20
Programmable logic device with delay-locked loop Grant 6,191,613 - Schultz , et al. February 20, 2	2001-02-20
FPGA configuration circuit including bus-based CRC register Grant 6,191,614 - Schultz , et al. February 20, 2	2001-02-20
Multiplexer array with shifted input traces Grant 6,097,210 - Iwanczuk , et al. August 1, 2	2000-08-01
FPGA having fast configuration memory data readback Grant 6,069,489 - Iwanczuk , et al. May 30, 2	2000-05-30
Method and apparatus for obtaining and using antifuse testing information to increase programmable device yield Grant 5,815,404 - Goetting , et al. September 29, 1	1998-09-29
Method and system for measuring antifuse resistance Grant 5,694,047 - Goetting , et al. December 2, 1	1997-12-02
High speed post-programming net packing method Grant 5,672,966 - Palczewski , et al. September 30, 1	1997-09-30
Low current optional inverter Grant 5,399,924 - Goetting , et al. March 21, 1	1995-03-21

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