Schroegmeier; Peter

Patent Applications and Registrations

Patent applications and USPTO patent grants for Schroegmeier; Peter.The latest application filed is for "method and integrated circuit for determining the state of a resistivity changing memory cell".

Company Profile

0.13.20

Schroegmeier; Peter - Munich DE
Schroegmeier; Peter - Munchen DE
Schroegmeier; Peter - Muenchen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Systems and methods for writing to a memory Grant 7,969,806 - De Ambroggi , et al. June 28, 2	2011-06-28
Apparatus and method for determining a memory state of a resistive n-level memory cell and memory device Grant 7,876,598 - Schroegmeier , et al. January 25, 2	2011-01-25
Integrated circuit with Resistivity changing memory cells and methods of operating the same Grant 7,706,201 - Liaw , et al. April 27, 2	2010-04-27
Method And Integrated Circuit For Determining The State Of A Resistivity Changing Memory Cell App 20090273967 - Schroegmeier; Peter ; et al.	2009-11-05
Memory Device With Different Types Of Phase Change Memory App 20090268513 - De Ambroggi; Luca ; et al.	2009-10-29
Systems and Methods for Writing to a Memory App 20090268532 - De Ambroggi; Luca ; et al.	2009-10-29
Apparatus and Method for Determining a Memory State of a Resistive N-Level Memory Cell and Memory Device App 20090219756 - Schroegmeier; Peter ; et al.	2009-09-03
Apparatus and method of operating an integrated circuit Grant 7,583,546 - Dietrich , et al. September 1, 2	2009-09-01
Integrated Circuit Including Memory Having Limited Read App 20090046499 - Philipp; Jan Boris ; et al.	2009-02-19
Method of Operating an Integrated Circuit, Integrated Circuit, and Memory Module App 20090021976 - Liaw; Corvin ; et al.	2009-01-22
Apparatus and Method of Operating an Integrated Circuit Technical Field App 20080304339 - Dietrich; Stefan ; et al.	2008-12-11
Emulated Combination Memory Device App 20080306723 - De Ambroggi; Luca ; et al.	2008-12-11
Read latency control circuit Grant 7,404,018 - Dietrich , et al. July 22, 2	2008-07-22
Method and circuit arrangement for controlling write access to a semiconductor memory Grant 7,224,625 - Dietrich , et al. May 29, 2	2007-05-29
Parallel-serial converter Grant 7,215,263 - Dietrich , et al. May 8, 2	2007-05-08
Device for driving a memory cell of a memory module by means of a charge store Grant 7,012,843 - Schroegmeier , et al. March 14, 2	2006-03-14
Test apparatus for testing an integrated circuit App 20050273678 - Dietrich, Stefan ; et al.	2005-12-08
Read latency control circuit App 20050270852 - Dietrich, Stefan ; et al.	2005-12-08
Method and circuit arrangement for controlling write access to a semiconductor memory App 20050254307 - Dietrich, Stefan ; et al.	2005-11-17
Integrated circuit with parallel-serial converter App 20050219084 - Dietrich, Stefan ; et al.	2005-10-06
Parallel-serial converter App 20050216623 - Dietrich, Stefan ; et al.	2005-09-29
Register for the parallel-serial conversion of data Grant 6,948,014 - Dietrich , et al. September 20, 2	2005-09-20
Latency time circuit for an S-DRAM Grant 6,819,624 - Acharya , et al. November 16, 2	2004-11-16
DDR memory and storage method Grant 6,731,567 - Acharya , et al. May 4, 2	2004-05-04
Control circuit for an S-DRAM Grant 6,717,886 - Pramod , et al. April 6, 2	2004-04-06
Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits Grant 6,670,802 - Dietrich , et al. December 30, 2	2003-12-30
Register for the parallel-serial conversion of data App 20030188064 - Dietrich, Stefan ; et al.	2003-10-02
Latency Time Circuit For An S-dram App 20030174550 - Acharya, Pramod ; et al.	2003-09-18
Control circuit for an S-DRAM App 20030161210 - Acharya, Pramod ; et al.	2003-08-28
DDR memory and storage method App 20030151971 - Acharya, Pramod ; et al.	2003-08-14
Device for driving a memory cell of a memory module App 20030002354 - Schroegmeier, Peter ; et al.	2003-01-02
Integrated memory having a row access controller for activating and deactivating row lines App 20020141279 - Dietrich, Stefan ; et al.	2002-10-03
Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits App 20020133750 - Dietrich, Stefan ; et al.	2002-09-19

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.