loadpatents
name:-0.0057549476623535
name:-0.0061969757080078
name:-0.00036311149597168
Schley; Jan-Malte Patent Filings

Schley; Jan-Malte

Patent Applications and Registrations

Patent applications and USPTO patent grants for Schley; Jan-Malte.The latest application filed is for "evaluation circuit and evaluation method for the assessment of memory cell states".

Company Profile
0.5.8
  • Schley; Jan-Malte - Munich DE
  • Schley; Jan-Malte - Dresden DE
  • Schley; Jan-Malte - Muenchen DE
  • Schley; Jan-Malte - Munchen DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Measuring circuit and reading method for memory cells
Grant 7,646,647 - Kern , et al. January 12, 2
2010-01-12
Evaluation circuit and evaluation method for the assessment of memory cell states
Grant 7,616,492 - Kern , et al. November 10, 2
2009-11-10
Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories
Grant 7,411,837 - Deppe , et al. August 12, 2
2008-08-12
Evaluation circuit and evaluation method for the assessment of memory cell states
App 20070086241 - Kern; Thomas ;   et al.
2007-04-19
Measuring circuit and reading method for memory cells
App 20070086240 - Kern; Thomas ;   et al.
2007-04-19
Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories
App 20070058443 - Deppe; Joachim ;   et al.
2007-03-15
Charge-trapping memory device
Grant 7,144,776 - Mikalo , et al. December 5, 2
2006-12-05
Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories
Grant 7,145,807 - Deppe , et al. December 5, 2
2006-12-05
Charge-trapping Memory Device
App 20060267078 - Mikalo; Ricardo Pablo ;   et al.
2006-11-30
Method of production of charge-trapping memory devices
App 20060223267 - Machill; Stefan ;   et al.
2006-10-05
Semiconductor device and method for fabricating a region thereon
App 20060054964 - Isler; Mark ;   et al.
2006-03-16
Isolation trench arrangement
App 20050275059 - Mikalo, Ricardo Pablo ;   et al.
2005-12-15
Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories
App 20050195650 - Deppe, Joachim ;   et al.
2005-09-08

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed