Schlegel; Peer
Patent Applications and Registrations
Patent applications and USPTO patent grants for Schlegel; Peer.The latest application filed is for "integrated circuit having a memory with a plurality of storage cells of synchronous design and connected to clock gating units".
- Schlegel; Peer - Chemnitz DE
| Patent | Date |
|---|---|
| Integrated Circuit Having A Memory With A Plurality Of Storage Cells Of Synchronous Design And Connected To Clock Gating Units App 20090195280 - Schlegel; Peer ; et al. | 2009-08-06 |
| Segmented on-chip memory and requester arbitration Grant 7,461,191 - Baer , et al. December 2, 2 | 2008-12-02 |
| Segmented on-chip memory and requester arbitration App 20060047910 - Baer; Matthias ; et al. | 2006-03-02 |
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