Schiekofer; Manfred

Patent Applications and Registrations

Patent applications and USPTO patent grants for Schiekofer; Manfred.The latest application filed is for "controlling an epitaxial growth process in an epitaxial reactor".

Company Profile

0.12.13

Schiekofer; Manfred - Freising N/A DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Controlling an epitaxial growth process in an epitaxial reactor Grant 9,090,991 - Schiekofer , et al. July 28, 2	2015-07-28
Method of controlling an epitaxial growth process in an epitaxial reactor Grant 8,940,093 - Schiekofer , et al. January 27, 2	2015-01-27
Method of forming an electrical contact between a support wafer and the surface of a top silicon layer of a silicon-on-insulator wafer and an electrical device including such an electrical contact Grant 8,932,942 - Steinmann , et al. January 13, 2	2015-01-13
Bipolar transistor Grant 8,330,223 - Schimpf , et al. December 11, 2	2012-12-11
Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection Grant 8,294,218 - El-Kareh , et al. October 23, 2	2012-10-23
Control of dopant diffusion from buried layers in bipolar integrated circuits Grant 8,247,300 - Babcock , et al. August 21, 2	2012-08-21
Controlling An Epitaxial Growth Process In An Epitaxial Reactor App 20120035768 - Schiekofer; Manfred ; et al.	2012-02-09
Bipolar Transistor App 20110049517 - SCHIMPF; Klaus ; et al.	2011-03-03
Method of Fabricating an Integrated Circuit with Gate Self-Protection, and an Integrated Circuit with Gate Self-Protection App 20100308416 - EL-KAREH; Badih ; et al.	2010-12-09
Control Of Dopant Diffusion From Buried Layers In Bipolar Integrated Circuits App 20100279481 - Babcock; Jeffrey A. ; et al.	2010-11-04
Method of Forming an Electrical Contact Between a Support Wafer and the Surface of a Top Silicon Layer of a Silicon-on-Insulator Wafer and an Electrical Device Including Such an Electrical Contact App 20100244184 - STEINMANN; Philipp ; et al.	2010-09-30
Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection Grant 7,772,057 - El-Kareh , et al. August 10, 2	2010-08-10
Method Of Controlling An Epitaxial Growth Process In An Epitaxial Reactor App 20080251007 - Schiekofer; Manfred ; et al.	2008-10-16
Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer Grant 7,217,322 - Babcock , et al. May 15, 2	2007-05-15
Method of Fabricating an Integrated Circuit with Gate Self-Protection, and an Integrated Circuit with Gate Self-Protection App 20070057281 - El-Kareh; Badih ; et al.	2007-03-15
Method of fabricating complementary bipolar transistors with SiGe base regions Grant 7,144,789 - El-Kareh , et al. December 5, 2	2006-12-05
Control of dopant diffusion from buried layers in bipolar integrated circuits App 20050250289 - Babcock, Jeffrey A. ; et al.	2005-11-10
Control of phosphorus profile by carbon in-situ doping for high performance vertical PNP transistor App 20050118771 - Yasuda, Hiroshi ; et al.	2005-06-02
Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer App 20050098093 - Babcock, Jeffrey A. ; et al.	2005-05-12
Method of fabricating complementary bipolar transistors with SiGe base regions App 20050014341 - El-Kareh, Badih ; et al.	2005-01-20
Control of dopant diffusion from buried layers in bipolar integrated circuits App 20030082882 - Babcock, Jeffrey A. ; et al.	2003-05-01
Reduced and atmospheric pressure process capable epitaxial chamber App 20020038689 - Bayer, Rudolf ; et al.	2002-04-04

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