Scherbinin; Sergey P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Scherbinin; Sergey P..The latest application filed is for "method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor".

Company Profile

5.5.10

Scherbinin; Sergey P. - Kaluga region RU
Scherbinin; Sergey P. - Obninsk RU

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture to enable speculative execution and avoid data corruption Grant 10,430,191 - Astigeyevich , et al. O	2019-10-01
Apparatus and methods to support counted loop exits in a multi-strand loop processor Grant 10,241,794 - Scherbinin , et al.	2019-03-26
Method to do control speculation on loads in a high performance strand-based loop accelerator Grant 10,241,789 - Ostanevich , et al.	2019-03-26
Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator Grant 10,241,801 - Iyer , et al.	2019-03-26
Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor Grant 10,235,171 - Ostanevich , et al.	2019-03-19
Apparatus And Methods Of Decomposing Loops To Improve Performance And Power Efficiency App 20180181398 - Scherbinin; Sergey P. ; et al.	2018-06-28
Method And Apparatus To Create Register Windows For Parallel Iterations To Achieve High Performance In Hw-sw Codesigned Loop Accelerator App 20180181405 - IYER; Jayesh ; et al.	2018-06-28
Apparatus And Methods To Support Counted Loop Exits In A Multi-strand Loop Processor App 20180181400 - Scherbinin; Sergey P. ; et al.	2018-06-28
Method And Apparatus To Efficiently Handle Allocation Of Memory Ordering Buffers In A Multi-strand Out-of-order Loop Processor App 20180181397 - OSTANEVICH; Alexander Y. ; et al.	2018-06-28
Method To Do Control Speculation On Loads In A High Performance Strand-based Loop Accelerator App 20180181396 - OSTANEVICH; Alexander Y. ; et al.	2018-06-28
Increasing Processor Instruction Window Via Seperating Instructions According To Criticality App 20170161075 - TITOV; ALEXANDR ; et al.	2017-06-08
Methods And Apparatus To Compile Instructions For A Vector Of Instruction Pointers Processor Architecture App 20150324200 - Astigeyevich; Yevgeniy M. ; et al.	2015-11-12
Methods And Apparatus To Compile Instructions For A Vector Of Instruction Pointers Processor Architecture App 20140281407 - Astigeyevich; Yevgeniy M. ; et al.	2014-09-18
Systems, Methods, And Apparatuses For Parallel Computing App 20100274972 - Babayan; Boris ; et al.	2010-10-28

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