Scheppler; Michael

Patent Applications and Registrations

Patent applications and USPTO patent grants for Scheppler; Michael.The latest application filed is for "memory read-out".

Company Profile

0.10.11

Scheppler; Michael - Munich DE
Scheppler; Michael - Grobenzell DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory read-out Grant 8,589,765 - Scheppler , et al. November 19, 2	2013-11-19
Memory Read-Out App 20130305124 - Scheppler; Michael ; et al.	2013-11-14
Memory read-out Grant 8,533,563 - Scheppler , et al. September 10, 2	2013-09-10
Integrated circuits having a controller to control a read operation and methods for operating the same Grant 7,864,579 - Gutsche , et al. January 4, 2	2011-01-04
Architecture of Function Blocks and Wirings in a Structured ASIC and Configurable Driver Cell of a Logic Cell Zone App 20100308863 - Gliese; Jorg ; et al.	2010-12-09
Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone Grant 7,755,110 - Gliese , et al. July 13, 2	2010-07-13
Integrated Circuits Having a Controller to Control a Read Operation and Methods for Operating the Same App 20100020610 - Gutsche; Jan ; et al.	2010-01-28
Memory Cell Arrangement and Method for Reading State Information From a Memory Cell Bypassing an Error Detection Circuit App 20090282308 - Gutsche; Jan ; et al.	2009-11-12
Memory Read-Out App 20090244973 - Scheppler; Michael ; et al.	2009-10-01
Circuit arrangement for supplying configuration data in FPGA devices Grant 7,492,187 - Kamp , et al. February 17, 2	2009-02-17
Mask-programmable logic macro and method for programming a logic macro Grant 7,439,765 - Kamp , et al. October 21, 2	2008-10-21
Configurable logic component without a local configuration memory and with a parallel configuration bus Grant 7,348,795 - Scheppler , et al. March 25, 2	2008-03-25
Look-up table Grant 7,323,904 - Veredas-Ramirez , et al. January 29, 2	2008-01-29
Logic circuit arrangement Grant 7,199,618 - Gliese , et al. April 3, 2	2007-04-03
Mask-programmable logic macro and method for programming a logic macro App 20060279329 - Kamp; Winfried ; et al.	2006-12-14
Circuit arrangement for supplying configuration data in FPGA devices App 20060273823 - Kamp; Winfried ; et al.	2006-12-07
Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone App 20050212562 - Gliese, Jorg ; et al.	2005-09-29
Configurable logic component without a local configuration memory and with a parallel configuration bus App 20050184755 - Scheppler, Michael ; et al.	2005-08-25
Look-up table App 20050174144 - Veredas-Ramirez, Francisco-Javier ; et al.	2005-08-11
Logic circuit arrangement App 20050134317 - Gliese, Jorg ; et al.	2005-06-23

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