| Patent | Date |
|---|
Transistors and methods of forming transistors using vertical nanowires
Grant 11,233,137 - Schepis , et al. January 25, 2 | 2022-01-25 |
Transistors And Methods Of Forming Transistors Using Vertical Nanowires
App 20200185510 - SCHEPIS; Dominic J. ; et al. | 2020-06-11 |
Transistor structure with varied gate cross-sectional area
Grant 10,680,085 - Schepis , et al. | 2020-06-09 |
Transistors and methods of forming transistors using vertical nanowires
Grant 10,658,494 - Schepis , et al. | 2020-05-19 |
Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step
Grant 10,643,907 - Kerber , et al. | 2020-05-05 |
Fin replacement in a field-effect transistor
Grant 10,453,959 - Cheng , et al. Oc | 2019-10-22 |
Low-cost SOI FinFET technology
Grant 10,438,858 - Bedell , et al. O | 2019-10-08 |
Structure And Method For Tensile And Compressive Strained Silicon Germanium With Same Germanium Concentration By Single Epitaxy
App 20190157167 - Kerber; Pranita ; et al. | 2019-05-23 |
Fin cut without residual fin defects
Grant 10,211,320 - Cheng , et al. Feb | 2019-02-19 |
Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step
Grant 10,204,837 - Kerber , et al. Feb | 2019-02-12 |
Low Defect Iii-v Semiconductor Template On Porous Silicon
App 20190043956 - de Souza; Joel P. ; et al. | 2019-02-07 |
Semiconductor structure having insulator pillars and semiconductor material on substrate
Grant 10,199,220 - Reznicek , et al. Fe | 2019-02-05 |
Fin field-effect transistor having an oxide layer under one or more of the plurality of fins
Grant 10,177,168 - Cheng , et al. J | 2019-01-08 |
Transistors And Methods Of Forming Transistors Using Vertical Nanowires
App 20180233583 - SCHEPIS; Dominic J. ; et al. | 2018-08-16 |
Structure And Method For Tensile And Compressive Strained Silicon Germanium With Same Germanium Concentration By Single Epitaxy Step
App 20180233418 - Kerber; Pranita ; et al. | 2018-08-16 |
Low defect III-V semiconductor template on porous silicon
Grant 10,032,870 - de Souza , et al. July 24, 2 | 2018-07-24 |
Transistor Structure With Varied Gate Cross-sectional Area
App 20180190797 - Schepis; Dominic J. ; et al. | 2018-07-05 |
Semiconductor Structure Having Insulator Pillars And Semiconductor Material On Substrate
App 20180190483 - Reznicek; Alexander ; et al. | 2018-07-05 |
Local SOI fins with multiple heights
Grant 10,014,322 - Cheng , et al. July 3, 2 | 2018-07-03 |
FinFET having highly doped source and drain regions
Grant 10,002,948 - Cheng , et al. June 19, 2 | 2018-06-19 |
Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step
Grant 10,002,798 - Kerber , et al. June 19, 2 | 2018-06-19 |
Preventing shorting between source and/or drain contacts and gate
Grant 9,972,620 - Surisetty , et al. May 15, 2 | 2018-05-15 |
Transistor structure with varied gate cross-sectional area
Grant 9,966,457 - Schepis , et al. May 8, 2 | 2018-05-08 |
FinFET having highly doped source and drain regions
Grant 9,935,181 - Cheng , et al. April 3, 2 | 2018-04-03 |
Low-cost Soi Finfet Technology
App 20180082910 - Bedell; Stephen W. ; et al. | 2018-03-22 |
Low-cost SOI FinFET technology
Grant 9,899,274 - Bedell , et al. February 20, 2 | 2018-02-20 |
Preventing Shorting Between Source And/or Drain Contacts And Gate
App 20180047727 - SURISETTY; Charan V. ; et al. | 2018-02-15 |
Methods of forming uniform and pitch independent fin recess
Grant 9,875,939 - Ke , et al. January 23, 2 | 2018-01-23 |
Fin Cut Without Residual Fin Defects
App 20170358656 - Cheng; Kangguo ; et al. | 2017-12-14 |
Contact formation for stacked FinFETs
Grant 9,812,575 - Reznicek , et al. November 7, 2 | 2017-11-07 |
Semiconductor structure having insulator pillars and semiconductor material on substrate
Grant 9,793,113 - Reznicek , et al. October 17, 2 | 2017-10-17 |
Semiconductor Structure Having Insulator Pillars And Semiconductor Material On Substrate
App 20170271146 - Reznicek; Alexander ; et al. | 2017-09-21 |
Transistor Structure With Varied Gate Cross-sectional Area
App 20170271483 - Schepis; Dominic J. ; et al. | 2017-09-21 |
Method and structure to form tensile strained SiGe fins and compressive strained SiGe fins on a same substrate
Grant 9,754,941 - Cheng , et al. September 5, 2 | 2017-09-05 |
finFET having highly doped source and drain regions
Grant 9,735,257 - Cheng , et al. August 15, 2 | 2017-08-15 |
Almost defect-free active channel region
Grant 9,728,626 - Schepis , et al. August 8, 2 | 2017-08-08 |
Fin cut without residual fin defects
Grant 9,722,052 - Cheng , et al. August 1, 2 | 2017-08-01 |
Structure And Method For Tensile And Compressive Strained Silicon Germanium With Same Germanium Concentration By Single Epitaxy Step
App 20170207136 - Kerber; Pranita ; et al. | 2017-07-20 |
Local Soi Fins With Multiple Heights
App 20170179163 - Cheng; Kangguo ; et al. | 2017-06-22 |
Fabrication Of Higher-k Dielectrics
App 20170170077 - Chudzik; Michael P. ; et al. | 2017-06-15 |
Silicon-on-insulator fin field-effect transistor device formed on a bulk substrate
Grant 9,679,763 - Cheng , et al. June 13, 2 | 2017-06-13 |
Fabrication of higher-K dielectrics
Grant 9,673,108 - Chudzik , et al. June 6, 2 | 2017-06-06 |
Fin Replacement In A Field-effect Transistor
App 20170148916 - Cheng; Kangguo ; et al. | 2017-05-25 |
Silicon-on-insulator Fin Field-effect Transistor Device Formed On A Bulk Substrate
App 20170148629 - Cheng; Kangguo ; et al. | 2017-05-25 |
Fin replacement in a field-effect transistor
Grant 9,660,059 - Cheng , et al. May 23, 2 | 2017-05-23 |
Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step
Grant 9,647,119 - Kerber , et al. May 9, 2 | 2017-05-09 |
Fin Cut Without Residual Fin Defects
App 20170117382 - Cheng; Kangguo ; et al. | 2017-04-27 |
Method for improving boron diffusion in a germanium-rich fin through germanium concentration reduction in fin S/D regions by thermal mixing
Grant 9,634,142 - Schepis , et al. April 25, 2 | 2017-04-25 |
SOI based FINFET with strained source-drain regions
Grant 9,601,624 - Bedell , et al. March 21, 2 | 2017-03-21 |
Local SOI fins with multiple heights
Grant 9,590,077 - Cheng , et al. March 7, 2 | 2017-03-07 |
Finfet Having Highly Doped Source And Drain Regions
App 20170005177 - Cheng; Kangguo ; et al. | 2017-01-05 |
Lateral bipolar junction transistor having graded SiGe base
Grant 9,525,027 - Hashemi , et al. December 20, 2 | 2016-12-20 |
Method And Structure To Form Tensile Strained Sige Fins And Compressive Strained Sige Fins On A Same Substrate
App 20160358922 - Cheng; Kangguo ; et al. | 2016-12-08 |
Implant-free punch through doping layer formation for bulk FinFET structures
Grant 9,514,995 - Fogel , et al. December 6, 2 | 2016-12-06 |
Implant-free Punch Through Doping Layer Formation For Bulk Finfet Structures
App 20160343623 - Fogel; Keith E. ; et al. | 2016-11-24 |
Local Soi Fins With Multiple Heights
App 20160336428 - Cheng; Kangguo ; et al. | 2016-11-17 |
Fabrication of higher-k dielectrics
Grant 9,478,425 - Chudzik , et al. October 25, 2 | 2016-10-25 |
Semiconductor junction formation
Grant 9,478,642 - Hashemi , et al. October 25, 2 | 2016-10-25 |
Methods of forming FinFET with wide unmerged source drain EPI
Grant 9,472,470 - Cheng , et al. October 18, 2 | 2016-10-18 |
Uniform depth fin trench formation
Grant 9,472,460 - Reznicek , et al. October 18, 2 | 2016-10-18 |
Embedded dynamic random access memory field effect transistor device
Grant 9,466,602 - Basker , et al. October 11, 2 | 2016-10-11 |
Embedded dynamic random access memory field effect transistor device
Grant 9,461,052 - Basker , et al. October 4, 2 | 2016-10-04 |
Silicon-germanium fin of height above critical thickness
Grant 9,455,141 - Cheng , et al. September 27, 2 | 2016-09-27 |
Low-cost Soi Finfet Technology
App 20160276226 - Bedell; Stephen W. ; et al. | 2016-09-22 |
FinFET having highly doped source and drain regions
Grant 9,450,079 - Cheng , et al. September 20, 2 | 2016-09-20 |
Integrated Strained Fin And Relaxed Fin
App 20160268378 - Hashemi; Pouya ; et al. | 2016-09-15 |
Low Defect Iii-v Semiconductor Template On Porous Silicon
App 20160268123 - de Souza; Joel P. ; et al. | 2016-09-15 |
Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step
Grant 9,443,873 - Kerber , et al. September 13, 2 | 2016-09-13 |
Silicon--germanium (SiGe) fin formation
Grant 9,390,925 - Cheng , et al. July 12, 2 | 2016-07-12 |
Strained semiconductor trampoline
Grant 9,391,198 - Kerber , et al. July 12, 2 | 2016-07-12 |
Method and structure to make fins with different fin heights and no topography
Grant 9,385,023 - Cheng , et al. July 5, 2 | 2016-07-05 |
Soi Based Finfet With Strained Source-drain Regions
App 20160190302 - Bedell; Stephen W. ; et al. | 2016-06-30 |
Silicon-germanium Fin Of Height Above Critical Thickness
App 20160181095 - Cheng; Kanggou ; et al. | 2016-06-23 |
SILICON-GERMANIUM (SiGe) FIN FORMATION
App 20160181105 - Cheng; Kangguo ; et al. | 2016-06-23 |
Fin Replacement In A Field-effect Transistor
App 20160172462 - Cheng; Kangguo ; et al. | 2016-06-16 |
Forming fins of different materials on the same substrate
Grant 9,368,492 - Cheng , et al. June 14, 2 | 2016-06-14 |
Double diamond shaped unmerged epitaxy for tall fins in tight pitch
Grant 9,368,512 - Cheng , et al. June 14, 2 | 2016-06-14 |
Finfet With Wide Unmerged Source Drain Epi
App 20160163826 - CHENG; Kangguo ; et al. | 2016-06-09 |
Silicon-on-nothing FinFETs
Grant 9,343,550 - Cheng , et al. May 17, 2 | 2016-05-17 |
Semiconductor Junction Formation
App 20160133727 - Hashemi; Pouya ; et al. | 2016-05-12 |
Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings
Grant 9,305,883 - Naczas , et al. April 5, 2 | 2016-04-05 |
Strained Semiconductor Trampoline
App 20160079419 - Kerber; Pranita ; et al. | 2016-03-17 |
Finfet Having Highly Doped Source And Drain Regions
App 20160035858 - Cheng; Kangguo ; et al. | 2016-02-04 |
Finfet Having Highly Doped Source And Drain Regions
App 20160035877 - Cheng; Kangguo ; et al. | 2016-02-04 |
FinFET device containing a composite spacer structure
Grant 9,236,397 - Holt , et al. January 12, 2 | 2016-01-12 |
Stacked semiconductor device
Grant 9,224,811 - Cheng , et al. December 29, 2 | 2015-12-29 |
Finfet Having Highly Doped Source And Drain Regions
App 20150295087 - Cheng; Kangguo ; et al. | 2015-10-15 |
Single-crystal Source-drain Merged By Polycrystalline Material
App 20150270332 - Harley; Eric C. ; et al. | 2015-09-24 |
LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING GRADED SiGe BASE
App 20150263091 - Hashemi; Pouya ; et al. | 2015-09-17 |
Stacked Semiconductor Device
App 20150263088 - Cheng; Kangguo ; et al. | 2015-09-17 |
Single crystal source-drain merged by polycrystalline material
Grant 9,123,826 - Harley , et al. September 1, 2 | 2015-09-01 |
Diamond Shaped Epitaxy
App 20150228761 - Cheng; Kangguo ; et al. | 2015-08-13 |
FinFET DEVICE CONTAINING A COMPOSITE SPACER STRUCTURE
App 20150221676 - Holt; Judson R. ; et al. | 2015-08-06 |
Silicon-on-nothing Finfets
App 20150194507 - Cheng; Kangguo ; et al. | 2015-07-09 |
Locally Raised Epitaxy For Improved Contact By Local Silicon Capping During Trench Silicide Processings
App 20150179576 - Naczas; Sebastian ; et al. | 2015-06-25 |
Silicon-on-nothing FinFETs
Grant 9,041,062 - Cheng , et al. May 26, 2 | 2015-05-26 |
Forming Fins Of Different Materials On The Same Substrate
App 20150102454 - Cheng; Kangguo ; et al. | 2015-04-16 |
Finfet With Relaxed Silicon-germanium Fins
App 20150097270 - Bedell; Stephen W. ; et al. | 2015-04-09 |
Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings
Grant 8,999,779 - Naczas , et al. April 7, 2 | 2015-04-07 |
Silicon-on-nothing Finfets
App 20150076561 - Cheng; Kangguo ; et al. | 2015-03-19 |
Locally Raised Epitaxy For Improved Contact By Local Silicon Capping During Trench Silicide Processings
App 20150069531 - Naczas; Sebastian ; et al. | 2015-03-12 |
Method of fabricating isolated capacitors and structure thereof
Grant 8,963,283 - Kwon , et al. February 24, 2 | 2015-02-24 |
Method of fabricating isolated capacitors and structure thereof
Grant 8,940,617 - Kwon , et al. January 27, 2 | 2015-01-27 |
Method Of Fabricating Isolated Capacitors And Structure Thereof
App 20140210039 - KWON; Oh-Jung ; et al. | 2014-07-31 |
Method of fabricating isolated capacitors and structure thereof
Grant 8,716,776 - Kwon , et al. May 6, 2 | 2014-05-06 |
Epitaxial growth of silicon doped with carbon and phosphorus using hydrogen carrier gas
Grant 8,685,845 - Dube , et al. April 1, 2 | 2014-04-01 |
Silicon-on-insulator substrate with built-in substrate junction
Grant 8,685,806 - Dyer , et al. April 1, 2 | 2014-04-01 |
Method of Fabricating Isolated Capacitors and Structure Thereof
App 20140080281 - KWON; Oh-Jung ; et al. | 2014-03-20 |
Method of fabricating isolated capacitors and structure thereof
Grant 8,652,925 - Kwon , et al. February 18, 2 | 2014-02-18 |
Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering
Grant 8,575,655 - Bedell , et al. November 5, 2 | 2013-11-05 |
Silicon-on-insulator Substrate With Built-in Substrate Junction
App 20130273715 - Dyer; Thomas W. ; et al. | 2013-10-17 |
Silicon-on-insulator substrate with built-in substrate junction
Grant 8,482,009 - Dyer , et al. July 9, 2 | 2013-07-09 |
Stressed Transistor With Improved Metastability
App 20130134444 - Adam; Thomas N. ; et al. | 2013-05-30 |
Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering
Grant 8,440,547 - Bedell , et al. May 14, 2 | 2013-05-14 |
Silicon germanium film formation method and structure
Grant 8,389,352 - Chakravarti , et al. March 5, 2 | 2013-03-05 |
Stressed transistor with improved metastability
Grant 8,361,859 - Adam , et al. January 29, 2 | 2013-01-29 |
Silicon Germanium Film Formation Method And Structure
App 20130009211 - Chakravarti; Ashima B. ; et al. | 2013-01-10 |
Method of Fabricating Isolated Capacitors and Structure Thereof
App 20120267754 - KWON; Oh-Jung ; et al. | 2012-10-25 |
METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE
App 20120228716 - Harley; Eric C. T. ; et al. | 2012-09-13 |
Silicon Germanium Film Formation Method And Structure
App 20120205749 - Chakravarti; Ashima B. ; et al. | 2012-08-16 |
Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure
Grant 8,232,186 - Harley , et al. July 31, 2 | 2012-07-31 |
METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING
App 20120181631 - Bedell; Stephen W. ; et al. | 2012-07-19 |
Stressed Transistor With Improved Metastability
App 20120112208 - ADAM; THOMAS N. ; et al. | 2012-05-10 |
Process for epitaxially growing epitaxial material regions
Grant 8,173,524 - Chakravarti , et al. May 8, 2 | 2012-05-08 |
Fabrication of SOI with gettering layer
Grant 8,128,749 - Lee , et al. March 6, 2 | 2012-03-06 |
Epitaxial Growth Of Silicon Doped With Carbon And Phosphorus Using Hydrogen Carrier Gas
App 20120043556 - Dube; Abhishek ; et al. | 2012-02-23 |
Method of Fabricating Isolated Capacitors and Structure Thereof
App 20120012971 - KWON; Oh-Jung ; et al. | 2012-01-19 |
Silicon-on-insulator Substrate With Built-in Substrate Junction
App 20110193149 - Dyer; Thomas Walter ; et al. | 2011-08-11 |
Semiconductor-on-insulator substrate with a diffusion barrier
Grant 7,955,950 - Lee , et al. June 7, 2 | 2011-06-07 |
Silicon-on-insulator substrate with built-in substrate junction
Grant 7,955,940 - Dyer , et al. June 7, 2 | 2011-06-07 |
Silicon-on-insulator Substrate With Built-in Substrate Junction
App 20110049594 - Dyer; Thomas Walter ; et al. | 2011-03-03 |
Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure
Grant 7,781,273 - Schepis , et al. August 24, 2 | 2010-08-24 |
Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer
Grant 7,781,800 - Chen , et al. August 24, 2 | 2010-08-24 |
METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING
App 20100200937 - Bedell; Stephen W. ; et al. | 2010-08-12 |
Pattern independent Si:C selective epitaxy
Grant 7,759,213 - Dube , et al. July 20, 2 | 2010-07-20 |
Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance
Grant 7,682,915 - Chen , et al. March 23, 2 | 2010-03-23 |
PATTERN INDEPENDENT Si:C SELECTIVE EPITAXY
App 20100035419 - DUBE; ABHISHEK ; et al. | 2010-02-11 |
METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE
App 20090294801 - Harley; Eric C. T. ; et al. | 2009-12-03 |
Sige channel epitaxial development for high-k PFET manufacturability
Grant 7,622,341 - Chudzik , et al. November 24, 2 | 2009-11-24 |
Method For Forming Carbon Silicon Alloy (csa) And Structures Thereof
App 20090267118 - Chakravarti; Ashima B. ; et al. | 2009-10-29 |
Polygrain Engineering By Adding Impurities In The Gas Phase During Chemical Vapor Deposition Of Polysilicon
App 20090269926 - Dube; Abhishek ; et al. | 2009-10-29 |
Sige Channel Epitaxial Development For High-k Pfet Manufacturability
App 20090181507 - Chudzik; Michael P. ; et al. | 2009-07-16 |
Method And Structure For Semiconductor Devices With Silicon-germanium Deposits
App 20090152590 - Adam; Thomas N. ; et al. | 2009-06-18 |
Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure
Grant 7,544,994 - Schepis , et al. June 9, 2 | 2009-06-09 |
Semiconductor-on-insulator Substrate With A Diffusion Barrier
App 20090102026 - Lee; Junedong ; et al. | 2009-04-23 |
Fabrication Of Soi With Gettering Layer
App 20090092810 - Lee; Junedong ; et al. | 2009-04-09 |
Manufacturable recessed strained RSD structure and process for advanced CMOS
Grant 7,446,005 - Messenger , et al. November 4, 2 | 2008-11-04 |
Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer
Grant 7,446,350 - Chen , et al. November 4, 2 | 2008-11-04 |
Embedded Silicon Germanium Using A Double Buried Oxide Silicon-on-insulator Wafer
App 20080265281 - Chen; Huajie ; et al. | 2008-10-30 |
Semiconductor Structue With Multiple Fins Having Different Channel Region Heights And Method Of Forming The Semiconductor Structure
App 20080224258 - Schepis; Dominic J. ; et al. | 2008-09-18 |
Pre-epitaxial Disposable Spacer Integration Scheme With Very Low Temperature Selective Epitaxy For Enhanced Device Performance
App 20080199998 - Chen; Huajie ; et al. | 2008-08-21 |
Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance
Grant 7,381,623 - Chen , et al. June 3, 2 | 2008-06-03 |
Semiconductor Structure With Multiple Fins Having Different Channel Region Heights And Method Of Forming The Semiconductor Structure
App 20080122013 - Schepis; Dominic J. ; et al. | 2008-05-29 |
Silicon-on-insulator chip having an isolation barrier for reliability
Grant RE40,339 - Bolam , et al. May 27, 2 | 2008-05-27 |
Hybrid Crystallographic Surface Orientation Substrate Having One Or More Soi Regions And/or Bulk Semiconductor Regions
App 20080111189 - Lee; Junedong ; et al. | 2008-05-15 |
Hybrid crystallographic surface orientation substrate having one or more SOI regions and/or bulk semiconductor regions
Grant 7,348,633 - Lee , et al. March 25, 2 | 2008-03-25 |
Hybrid Crystallographic Surface Orientation Substrate Having One Or More Soi Regions And/or Bulk Semiconductor Regions
App 20070122634 - Lee; Junedong ; et al. | 2007-05-31 |
Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet
Grant 7,183,573 - Bryant , et al. February 27, 2 | 2007-02-27 |
SOI wafers with 30-100 .ANG. buried oxide (BOX) created by wafer bonding using 30-100 .ANG. thin oxide as bonding layer
Grant 7,166,521 - Boyd , et al. January 23, 2 | 2007-01-23 |
Embedded Silicon Germanium Using A Double Buried Oxide Silicon-on-insulator Wafer
App 20060255330 - Chen; Huajie ; et al. | 2006-11-16 |
Doped Nitride Film, Doped Oxide Film And Other Doped Films And Deposition Rate Improvement For Rtcvd Processes
App 20060237846 - Chakravarti; Ashima B. ; et al. | 2006-10-26 |
Patterning SOI with silicon mask to create box at different depths
Grant 7,115,463 - Sadana , et al. October 3, 2 | 2006-10-03 |
Semiconductor device having a strained raised source/drain
Grant 7,115,955 - Messenger , et al. October 3, 2 | 2006-10-03 |
Manufacturable recessed strained RSD structure and process for advanced CMOS
App 20060205189 - Messenger; Brian ; et al. | 2006-09-14 |
Patterning SOI with silicon mask to create box at different depths
App 20060040476 - Sadana; Devendra K. ; et al. | 2006-02-23 |
Manufacturable Recessed Strained Rsd Structure And Process For Advanced Cmos
App 20060022266 - Messenger; Brian ; et al. | 2006-02-02 |
A Manufacturable Method And Structure For Double Spacer Cmos With Optimized Nfet/pfet Performance
App 20050275034 - Deshpande, Sadanand V. ; et al. | 2005-12-15 |
High electrical quality buried oxide in simox
App 20050170570 - DeSouza, Joel P. ; et al. | 2005-08-04 |
Surface engineering to prevent epi growth on gate poly during selective epi processing
Grant 6,900,092 - Ajmera , et al. May 31, 2 | 2005-05-31 |
CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture
Grant 6,891,228 - Park , et al. May 10, 2 | 2005-05-10 |
Field effect transistor with stressed channel and method for making same
Grant 6,884,667 - Doris , et al. April 26, 2 | 2005-04-26 |
CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture
App 20050040465 - Park, Heemyong ; et al. | 2005-02-24 |
SOI wafers with 30-100 A buried oxide (BOX) created by wafer bonding using 30-100 A thin oxide as bonding layer
App 20050042841 - Boyd, Diane C. ; et al. | 2005-02-24 |
SOI wafers with 30-100 .ANG. buried oxide (BOX) created by wafer bonding using 30-100 .ANG. thin oxide as bonding layer
Grant 6,835,633 - Boyd , et al. December 28, 2 | 2004-12-28 |
CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture
Grant 6,828,630 - Park , et al. December 7, 2 | 2004-12-07 |
CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions
Grant 6,808,974 - Park , et al. October 26, 2 | 2004-10-26 |
CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture
App 20040129979 - Park, Heemyong ; et al. | 2004-07-08 |
SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
Grant 6,717,216 - Doris , et al. April 6, 2 | 2004-04-06 |
SOI wafers with 30-100 A buried oxide (box) created by wafer bonding using 30-100 A thin oxide as bonding layer
App 20040018699 - Boyd, Diane C. ; et al. | 2004-01-29 |
Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator
Grant 6,645,795 - Muller , et al. November 11, 2 | 2003-11-11 |
Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon
Grant 6,602,759 - Ajmera , et al. August 5, 2 | 2003-08-05 |
Silicon-on-insulator chip having an isolation barrier for reliability
Grant 6,563,173 - Bolam , et al. May 13, 2 | 2003-05-13 |
Method of forming a body contact using BOX modification
Grant 6,531,375 - Giewont , et al. March 11, 2 | 2003-03-11 |
Method of integrating substrate contact on SOI wafers with STI process
Grant 6,521,947 - Ajmera , et al. February 18, 2 | 2003-02-18 |
Method for forming notch gate having self-aligned raised source/drain structure
Grant 6,506,649 - Fung , et al. January 14, 2 | 2003-01-14 |
Surface engineering to prevent epi growth on gate poly during selective epi processing
App 20020192888 - Ajmera, Atul C. ; et al. | 2002-12-19 |
Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator
App 20020171105 - Muller, K. Paul ; et al. | 2002-11-21 |
CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions
App 20020173105 - Park, Heemyong ; et al. | 2002-11-21 |
Polysilicon doped transistor
App 20020162999 - Muller, K. Paul ; et al. | 2002-11-07 |
Method For Forming Notch Gate Having Self-aligned Raised Source/drain Structure
App 20020132431 - Fung, Ka Hing ; et al. | 2002-09-19 |
Surface engineering to prevent EPI growth on gate poly during selective EPI processing
Grant 6,440,807 - Ajmera , et al. August 27, 2 | 2002-08-27 |
Densely patterned silicon-on-insulator (SOI) region on a wafer
Grant 6,429,488 - Leobandung , et al. August 6, 2 | 2002-08-06 |
MOS transistors with raised sources and drains
Grant 6,429,084 - Park , et al. August 6, 2 | 2002-08-06 |
Low Dielectric Constant Sidewall Spacer Using Notch Gate Process
App 20020096695 - Ajmera, Atul C. ; et al. | 2002-07-25 |
Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon
App 20020072196 - Ajmera, Atul C. ; et al. | 2002-06-13 |
Fully amorphized source/drain for leaky junctions
Grant 6,395,587 - Crowder , et al. May 28, 2 | 2002-05-28 |
Thermal conductivity enhanced semiconductor structures and fabrication processes
Grant 6,387,742 - Gauthier, Jr. , et al. May 14, 2 | 2002-05-14 |
Disposable spacer for symmetric and asymmetric schottky contact to SOI mosfet
App 20020048841 - Bryant, Andres ; et al. | 2002-04-25 |
Silicon-on-insulator chip having an isolation barrier for reliability
App 20020043686 - Bolam, Ronald J. ; et al. | 2002-04-18 |
Multistack 3-dimensional high density semiconductor device and method for fabrication
App 20020000615 - Ma, William Hsioh-Lien ; et al. | 2002-01-03 |
Planar substrate with patterned silicon-on- insulator region and self-aligned trench
App 20010041395 - Ajmera, Atul ; et al. | 2001-11-15 |
Thermal conductivity enhanced semiconductor structures and fabrication processes
App 20010029084 - Gauthier, Robert J. JR. ; et al. | 2001-10-11 |
Silicon-on-insulator chip having an isolation barrier for reliability
App 20010024863 - Bolam, Ronald J. ; et al. | 2001-09-27 |
Thermal conductivity enhanced semiconductor structures and fabrication processes
Grant 6,288,426 - Gauthier, Jr. , et al. September 11, 2 | 2001-09-11 |
Densely patterned silicon-on-insulator (SOI) region on a wafer
App 20010008292 - Leobandung, Effendi ; et al. | 2001-07-19 |
Process of making densely patterned silicon-on-insulator (SOI) region on a wafer
Grant 6,214,694 - Leobandung , et al. April 10, 2 | 2001-04-10 |
Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture
Grant 6,133,610 - Bolam , et al. October 17, 2 | 2000-10-17 |
Process of etching an oxide layer
Grant 5,811,357 - Armacost , et al. September 22, 1 | 1998-09-22 |
Method of making a self cooling electrically programmable fuse
Grant 5,622,892 - Bezama , et al. April 22, 1 | 1997-04-22 |
Method of forming a thermally activated noise immune fuse
Grant 5,614,440 - Bezama , et al. March 25, 1 | 1997-03-25 |
Self cooling electrically programmable fuse
Grant 5,585,663 - Bezama , et al. December 17, 1 | 1996-12-17 |
Antifuse element with electrical or optical programming
Grant 5,485,032 - Schepis , et al. January 16, 1 | 1996-01-16 |
Self protective decoupling capacitor structure
Grant 5,394,294 - Mei , et al. February 28, 1 | 1995-02-28 |
Method for forming an antifuse element with electrical or optical programming
Grant 5,314,840 - Schepis , et al. May 24, 1 | 1994-05-24 |
Electrically programmable antifuse using metal penetration of a junction
Grant 5,298,784 - Gambino , et al. March 29, 1 | 1994-03-29 |
Fabricating planar complementary patterned subcollectors with silicon epitaxial layer
Grant 5,279,987 - Lechaton , et al. January 18, 1 | 1994-01-18 |
Method of making semiconductor device contact including transition metal-compound dopant source
Grant 5,086,016 - Brodsky , et al. February 4, 1 | 1992-02-04 |
BiCMOS process
Grant 4,960,726 - Lechaton , et al. October 2, 1 | 1990-10-02 |
Method of making defect free silicon islands using SEG
Grant 4,758,531 - Beyer , et al. July 19, 1 | 1988-07-19 |
Total dielectric isolation for integrated circuits
Grant 4,661,832 - Lechaton , et al. April 28, 1 | 1987-04-28 |
Total dielectric isolation for integrated circuits
Grant 4,502,913 - Lechaton , et al. March 5, 1 | 1985-03-05 |
| 