Scheer; Robert F.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Scheer; Robert F..The latest application filed is for "self-aligned npn transistor with raised extrinsic base".

Company Profile

0.7.7

Scheer; Robert F. - Portland OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-aligned NPN transistor with raised extrinsic base Grant 7,026,666 - Kalnitsky , et al. April 11, 2	2006-04-11
Method of forming a super self-aligned hetero-junction bipolar transistor Grant 6,861,324 - Kalnitsky , et al. March 1, 2	2005-03-01
Integrating multiple thin film resistors Grant 6,855,585 - Kalnitsky , et al. February 15, 2	2005-02-15
Method of forming self-aligned NPN transistor with raised extrinsic base Grant 6,767,798 - Kalnitsky , et al. July 27, 2	2004-07-27
Self-aligned NPN transistor with raised extrinsic base App 20040126978 - Kalnitsky, Alexander ; et al.	2004-07-01
Method of forming self-aligned bipolar transistor Grant 6,686,250 - Kalnitsky , et al. February 3, 2	2004-02-03
Self-aligned NPN transistor with raised extrinsic base App 20030189239 - Kalnitsky, Alexander ; et al.	2003-10-09
Method Of Forming An Integrated Inductor And High Speed Interconnect In A Planarized Process With Shallow Trench Isolation App 20030096487 - Kalnitsky, Alexander ; et al.	2003-05-22
Method Of Forming An Integrated Circuit On A Low Loss Substrate App 20030008441 - Kalnitsky, Alexander ; et al.	2003-01-09
Method for forming a super self-aligned hetero-junction bipolar transistor App 20020192894 - Kalnitsky, Alexander ; et al.	2002-12-19
Method of forming an integrated circuit on a low loss substrate Grant 6,489,217 - Kalnitsky , et al. December 3, 2	2002-12-03
Forming devices on a semiconductor substrate App 20020173092 - Yamaguchi, Tadanori ; et al.	2002-11-21
Method of forming an NPN device App 20020109208 - Kalnitsky, Alexander ; et al.	2002-08-15
Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates Grant 6,303,413 - Kalnitsky , et al. October 16, 2	2001-10-16

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