Schaefer; William Jeffrey
Patent Applications and Registrations
Patent applications and USPTO patent grants for Schaefer; William Jeffrey.The latest application filed is for "materials and structure for a high reliability bga connection between ltcc and pb boards".
- Schaefer; William Jeffrey - San Jose CA
- Schaefer; William Jeffrey - Dublin CA
| Patent | Date |
|---|---|
| Materials and structure for a high reliability BGA connection between LTCC and PB boards Grant 7,287,323 - Ehlert , et al. October 30, 2 | 2007-10-30 |
| Semiconductor wafer having a bottom surface protective coating Grant RE38,789 - Kao , et al. September 6, 2 | 2005-09-06 |
| Materials and structure for a high reliability bga connection between LTCC and PB boards Grant 6,800,815 - Ehlert , et al. October 5, 2 | 2004-10-05 |
| Semiconductor wafer having a bottom surface protective coating Grant 6,175,162 - Kao , et al. January 16, 2 | 2001-01-16 |
| Surface mount die: wafer level chip-scale package and process for making the same Grant 6,075,290 - Schaefer , et al. June 13, 2 | 2000-06-13 |
| Semiconductor wafer having a bottom surface protective coating Grant 6,023,094 - Kao , et al. February 8, 2 | 2000-02-08 |
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