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name:-0.053556203842163
name:-0.30610203742981
name:-0.010980129241943
Schaefer; Andre Patent Filings

Schaefer; Andre

Patent Applications and Registrations

Patent applications and USPTO patent grants for Schaefer; Andre.The latest application filed is for "shaft cover for shafts, channel entrances, or drainage channels".

Company Profile
4.46.63
  • Schaefer; Andre - Braunschweig DE
  • Schaefer; Andre - Ludwigshafen DE
  • SCHAEFER; Andre - Sasssenburg DE
  • Schaefer; Andre - Sassenburg DE
  • Schaefer; Andre - Portland OR
  • Schaefer; Andre - Munchen DE
  • Schaefer; Andre - Munich DE
  • Schaefer; Andre - Muenchen DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems
Grant 10,853,216 - Liu , et al. December 1, 2
2020-12-01
Shaft cover for shafts, channel entrances, or drainage channels
Grant 10,851,516 - Hensel , et al. December 1, 2
2020-12-01
Shaft Cover For Shafts, Channel Entrances, Or Drainage Channels
App 20190323199 - Hensel; Torsten ;   et al.
2019-10-24
Stacked Memory With Interface Providing Offset Interconnects
App 20190304953 - VOGT; Pete D. ;   et al.
2019-10-03
Power management in multi-die assemblies
Grant 10,079,489 - Droege , et al. September 18, 2
2018-09-18
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S
App 20180122779 - VOGT; Pete D. ;   et al.
2018-05-03
Integrated voltage regulators with magnetically enhanced inductors
Grant 9,921,640 - Zillmann , et al. March 20, 2
2018-03-20
Through-body-via isolated coaxial capacitor and techniques for forming same
Grant 9,911,689 - Lee , et al. March 6, 2
2018-03-06
Stacked memory with interface providing offset interconnects
Grant 9,768,148 - Vogt , et al. September 19, 2
2017-09-19
Through-body-via Isolated Coaxial Capacitor And Techniques For Forming Same
App 20170040255 - LEE; KEVIN J. ;   et al.
2017-02-09
Power Management In Multi-die Assemblies
App 20170011779 - Droege; Guido ;   et al.
2017-01-12
Data Reorder During Memory Access
App 20160306566 - Lu; Shih-Lien L. ;   et al.
2016-10-20
Techniques for accessing a dynamic random access memory array
Grant 9,472,249 - Schaefer , et al. October 18, 2
2016-10-18
Power management in multi-die assemblies
Grant 9,391,453 - Droege , et al. July 12, 2
2016-07-12
Configuration for power reduction in DRAM
Grant 9,361,970 - Schaefer , et al. June 7, 2
2016-06-07
Dynamically applying refresh overcharge voltage to extend refresh cycle time
Grant 9,311,983 - Schaefer April 12, 2
2016-04-12
Resonant clocking for three-dimensional stacked devices
Grant 9,287,196 - Saraswat , et al. March 15, 2
2016-03-15
Interlayer communications for 3D integrated circuit stack
Grant 9,263,422 - Droege , et al. February 16, 2
2016-02-16
Fully integrated voltage regulators for multi-stack integrated circuit architectures
Grant 9,229,466 - Saraswat , et al. January 5, 2
2016-01-05
Separate microchannel voltage domains in stacked memory architecture
Grant 9,230,614 - Schaefer , et al. January 5, 2
2016-01-05
Dynamically Applying Refresh Overcharge Voltage To Extend Refresh Cycle Time
App 20150380072 - SCHAEFER; ANDRE
2015-12-31
Techniques for Accessing a Dynamic Random Access Memory Array
App 20150357011 - SCHAEFER; ANDRE ;   et al.
2015-12-10
Mechanism For Facilitating Write Tracking For Following Data Eye Movements Across Changing Thermal Conditions In Memory Systems
App 20150317228 - LIU; Tsun Ho ;   et al.
2015-11-05
Techniques for accessing a dynamic random access memory array
Grant 9,135,982 - Schaefer , et al. September 15, 2
2015-09-15
Memory sense amplifier voltage modulation
Grant 9,087,559 - Schaefer July 21, 2
2015-07-21
Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems
Grant 9,086,881 - Liu , et al. July 21, 2
2015-07-21
Techniques for Accessing a Dynamic Random Access Memory Array
App 20150170729 - SCHAEFER; ANDRE ;   et al.
2015-06-18
Interlayer Communications For 3d Integrated Circuit Stack
App 20150130534 - Droege; Guido ;   et al.
2015-05-14
Adaptive address mapping with dynamic runtime memory mapping selection
Grant 9,026,767 - Schaefer , et al. May 5, 2
2015-05-05
Stacked Memory With Interface Providing Offset Interconnects
App 20150108660 - Vogt; Pete ;   et al.
2015-04-23
Interlayer communications for 3D integrated circuit stack
Grant 9,000,577 - Droege , et al. April 7, 2
2015-04-07
Stacked memory with interface providing offset interconnects
Grant 8,971,087 - Vogt , et al. March 3, 2
2015-03-03
System and method for accessing memory
Grant 8,959,271 - Schaefer February 17, 2
2015-02-17
Power Management In Multi-die Assemblies
App 20150003181 - Droege; Guido ;   et al.
2015-01-01
Configuration For Power Reduction In Dram
App 20140325136 - Schaefer; Andre ;   et al.
2014-10-30
System And Method For Accessing Memory
App 20140281193 - SCHAEFER; ANDRE
2014-09-18
Configuration for power reduction in DRAM
Grant 8,811,110 - Schaefer , et al. August 19, 2
2014-08-19
Resonant Clocking For Three-dimensional Stacked Devices
App 20140183691 - Saraswat; Ruchir ;   et al.
2014-07-03
Memory Sense Amplifier Voltage Modulation
App 20140185392 - Schaefer; Andre
2014-07-03
Integrated Voltage Regulators With Magnetically Enhanced Inductors
App 20140092574 - ZILLMANN; Uwe ;   et al.
2014-04-03
Configuration For Power Reduction In Dram
App 20140006700 - Schaefer; Andre ;   et al.
2014-01-02
Mechanism For Facilitating Write Tracking For Following Data Eye Movements Across Changing Thermal Conditions In Memory Systems
App 20140006702 - Liu; Tsun Ho ;   et al.
2014-01-02
Fully Integrated Voltage Regulators For Multi-stack Integrated Circuit Architectures
App 20130335059 - Saraswat; Ruchir ;   et al.
2013-12-19
Interlayer Communications For 3d Integrated Circuit Stack
App 20130293292 - Droege; Guido ;   et al.
2013-11-07
Separate Microchannel Voltage Domains In Stacked Memory Architecture
App 20130279276 - Schaefer; Andre
2013-10-24
Stacked Memory With Interface Providing Offset Interconnects
App 20130272049 - Vogt; Pete ;   et al.
2013-10-17
Energy efficient power distribution for 3D integrated circuit stack
Grant 8,547,769 - Saraswat , et al. October 1, 2
2013-10-01
Adaptive Address Mapping with Dynamic Runtime Memory Mapping Selection
App 20130246734 - Schaefer; Andre ;   et al.
2013-09-19
Efficient clocking scheme for a bidirectional data link
Grant 8,321,719 - Schaefer November 27, 2
2012-11-27
Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack
App 20120250443 - SARASWAT; RUCHIR ;   et al.
2012-10-04
Adaptive address mapping with dynamic runtime memory mapping selection
Grant 8,135,936 - Schaefer , et al. March 13, 2
2012-03-13
Fast data eye retraining for a memory
Grant 8,037,375 - Schaefer October 11, 2
2011-10-11
Adaptive Address Mapping With Dynamic Runtime Memory Mapping Selection
App 20110153908 - Schaefer; Andre ;   et al.
2011-06-23
Efficient Clocking Scheme For A Bidirectional Data Link
App 20110078368 - Schaefer; Andre
2011-03-31
Fast data eye retraining for a memory
App 20100332921 - Schaefer; Andre
2010-12-30
Method of transferring signals between a memory device and a memory controller
Grant 7,587,655 - Wallner , et al. September 8, 2
2009-09-08
Device in a memory circuit for definition of waiting times
Grant 7,355,921 - Schaefer , et al. April 8, 2
2008-04-08
Driver circuit for binary signals
Grant 7,321,240 - Schaefer January 22, 2
2008-01-22
Method of transferring signals between a memory device and a memory controller
App 20070091711 - Wallner; Paul ;   et al.
2007-04-26
Semiconductor memory system, semiconductor memory chip, and method of masking write data in a semiconductor memory chip
App 20070061494 - Wallner; Paul ;   et al.
2007-03-15
Differental current source for generating DRAM refresh signal
Grant 7,180,805 - Schnabel , et al. February 20, 2
2007-02-20
Semiconductor memory chip and method of protecting a memory core thereof
App 20070006057 - Wallner; Paul ;   et al.
2007-01-04
Device in a memory circuit for definition of waiting times
App 20060233005 - Schaefer; Andre ;   et al.
2006-10-19
Driver circuit for binary signals
App 20060170456 - Schaefer; Andre
2006-08-03
Circuit arrangement and method for setting operating parameters in a RAM module
App 20060152957 - Schaefer; Andre
2006-07-13
Circuit device with clock pulse detection facility
Grant 7,068,079 - Schaefer , et al. June 27, 2
2006-06-27
Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor device including at least one such arrangement
Grant 7,049,930 - Schnabel , et al. May 23, 2
2006-05-23
Memory circuit comprising an initialization unit, and method for optimizing data reception parameters in a memory controller
App 20060085705 - Schaefer; Andre
2006-04-20
Integrated semiconductor circuit and method for producing an integrated semiconductor circuit
App 20060049511 - Schaefer; Andre
2006-03-09
Semi-conductor component with clock relaying device
Grant 6,917,562 - Schaefer , et al. July 12, 2
2005-07-12
Integrated circuit
Grant 6,911,732 - Muff , et al. June 28, 2
2005-06-28
Wafer handling device
Grant 6,783,596 - Schaefer , et al. August 31, 2
2004-08-31
Integrated circuit
App 20040145036 - Muff, Simon ;   et al.
2004-07-29
Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor device including at least one such arrangement
App 20040130433 - Schnabel, Joachim ;   et al.
2004-07-08
Circuit device with clock pulse detection facility
App 20040124887 - Schaefer, Andre ;   et al.
2004-07-01
Semi-conductor component with clock relaying device
App 20040124886 - Schaefer, Andre ;   et al.
2004-07-01
Voltage supply for semiconductor memory
Grant 6,690,612 - Gall , et al. February 10, 2
2004-02-10
Differental current source for generating dram refresh signal
App 20040004867 - Schnabel, Joachim ;   et al.
2004-01-08
Method for masking DQ bits
Grant 6,625,065 - Gall , et al. September 23, 2
2003-09-23
Wafer handling device
App 20030033981 - Schaefer, Andre ;   et al.
2003-02-20
Evaluation device for assessing a digital data signal, in particular a data signal for a semiconductor memory circuit
App 20020196868 - Ruckerbauer, Hermann ;   et al.
2002-12-26
Voltage supply for semiconductor memory arrangement
App 20020141274 - Gall, Martin ;   et al.
2002-10-03
Method for masking DQ bits
App 20020076872 - Gall, Martin ;   et al.
2002-06-20

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