Saxena; Sharad

Patent Applications and Registrations

Patent applications and USPTO patent grants for Saxena; Sharad.The latest application filed is for "test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies".

Company Profile

2.18.3

Saxena; Sharad - Richardson TX
Saxena; Sharad - Dallas TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies Grant 10,852,337 - Saxena , et al. December 1, 2	2020-12-01
Method for applying charge-based-capacitance-measurement with switches using only NMOS or only PMOS transistors Grant 10,641,804 - Saxena	2020-05-05
Test structures and method for electrical measurement of FinFET fin height Grant 10,529,631 - Saxena , et al. J	2020-01-07
Method for accurate measurement of leaky capacitors using charge based capacitance measurements Grant 9,952,268 - Saxena , et al. April 24, 2	2018-04-24
Test Structures For Measuring Silicon Thickness In Fully Depleted Silicon-on-insulator Technologies App 20170309524 - Saxena; Sharad ; et al.	2017-10-26
Test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies Grant 9,691,669 - Saxena , et al. June 27, 2	2017-06-27
Systems and methods for detecting and monitoring nickel-silicide process and induced failures Grant 7,932,105 - Saxena , et al. April 26, 2	2011-04-26
Method for reducing layout printability effects on semiconductor device performance Grant 7,644,388 - Daldoss , et al. January 5, 2	2010-01-05
Method for optimizing the characteristics of integrated circuits components from circuit specifications Grant 7,047,505 - Saxena , et al. May 16, 2	2006-05-16
Methodology for the optimization of testing and diagnosis of analog and mixed signal ICs and embedded cores Grant 7,003,742 - Saxena , et al. February 21, 2	2006-02-21
Efficient method for modeling and simulation of the impact of local and global variation on integrated circuits Grant 6,978,229 - Saxena , et al. December 20, 2	2005-12-20
Method for optimizing the characteristics of integrated circuits components from circuit specifications App 20040064296 - Saxena, Sharad ; et al.	2004-04-01
Methodology for the optimization of testing and diagnosis of analog and mixed signal ICs and embedded cores App 20040015793 - Saxena, Sharad ; et al.	2004-01-22
Method and apparatus for predicting an operational lifetime of a transistor Grant 6,530,064 - Vasanth , et al. March 4, 2	2003-03-04
Method and system for using response-surface methodologies to determine optimal tuning parameters for complex simulators Grant 6,381,564 - Davis , et al. April 30, 2	2002-04-30
Design of microelectronic process flows for manufacturability and performance Grant 6,311,096 - Saxena , et al. October 30, 2	2001-10-30
Process flow design at the module effects level through the use of acceptability regions Grant 5,912,678 - Saxena , et al. June 15, 1	1999-06-15
Controlling process modules using site models and monitor wafer control Grant 5,751,582 - Saxena , et al. May 12, 1	1998-05-12
Method of diagnosing malfunctions in semiconductor manufacturing equipment Grant 5,642,296 - Saxena June 24, 1	1997-06-24
Use of spatial models for simultaneous control of various non-uniformity metrics Grant 5,546,312 - Mozumder , et al. August 13, 1	1996-08-13
Multi-variable statistical process controller for discrete manufacturing Grant 5,408,405 - Mozumder , et al. April 18, 1	1995-04-18

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