Savastiouk; Sergey

Patent Applications and Registrations

Patent applications and USPTO patent grants for Savastiouk; Sergey.The latest application filed is for "structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor".

Company Profile

0.31.32

Savastiouk; Sergey - Saratoga CA
Savastiouk; Sergey - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates Grant 9,589,879 - Kosenko , et al. March 7, 2	2017-03-07
Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor Grant 9,515,024 - Kosenko , et al. December 6, 2	2016-12-06
Structures formed using monocrystalline silicon and/or other materials for optical and other applications Grant 9,323,010 - Kosenko , et al. April 26, 2	2016-04-26
Structures With Through Vias Passing Through A Substrate Comprising A Planar Insulating Layer Between Semiconductor App 20150348843 - KOSENKO; Valentin ; et al.	2015-12-03
Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers Grant 9,142,511 - Kosenko , et al. September 22, 2	2015-09-22
Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques Grant 9,111,902 - Savastiouk , et al. August 18, 2	2015-08-18
Substrates With Through Vias With Conductive Features For Connection To Integrated Circuit Elements, And Methods For Forming Through Vias In Substrates App 20150228570 - KOSENKO; Valentin ; et al.	2015-08-13
Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates Grant 9,018,094 - Kosenko , et al. April 28, 2	2015-04-28
Structures With Through Vias Passing Through A Substrate Comprising A Planar Insulating Layer Between Semiconductor Layers App 20140346646 - KOSENKO; Valentin ; et al.	2014-11-27
Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers Grant 8,829,683 - Kosenko , et al. September 9, 2	2014-09-09
Optical interposer Grant 8,757,897 - Kosenko , et al. June 24, 2	2014-06-24
Dielectric Trenches, Nickel/tantalum Oxide Structures, And Chemical Mechanical Polishing Techniques App 20140131836 - Savastiouk; Sergey ; et al.	2014-05-15
Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques Grant 8,633,589 - Savastiouk , et al. January 21, 2	2014-01-21
Structures With Through Vias Passing Through A Substrate Comprising A Planar Insulating Layer Between Semiconductor Layers App 20130214429 - Kosenko; Valentin ; et al.	2013-08-22
Structures Formed Using Monocrystalline Silicon And/or Other Materials For Optical And Other Applications App 20130177274 - Kosenko; Valentin ; et al.	2013-07-11
Optical Interposer App 20130177281 - Kosenko; Valentin ; et al.	2013-07-11
Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers Grant 8,431,431 - Kosenko , et al. April 30, 2	2013-04-30
Structures With Through Vias Passing Through A Substrate Comprising A Planar Insulating Layer Between Semiconductor Layers App 20130015585 - Kosenko; Valentin ; et al.	2013-01-17
Substrates With Through Vias With Conductive Features For Connection To Integrated Circuit Elements, And Methods For Forming Through Vias In Substrates App 20120228778 - Kosenko; Valentin ; et al.	2012-09-13
Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques Grant 7,964,508 - Savastiouk , et al. June 21, 2	2011-06-21
Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby Grant 7,521,360 - Halahan , et al. April 21, 2	2009-04-21
Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques Grant 7,510,928 - Savastiouk , et al. March 31, 2	2009-03-31
Dielectric Trenches, Nickel/tantalum Oxide Structures, And Chemical Mechanical Polishing Techniques App 20080311749 - Savastiouk; Sergey ; et al.	2008-12-18
Bonding Of Structures Together Including, But Not Limited To, Bonding A Semiconductor Wafer To A Carrier App 20080305580 - Berger; Alexander J. ; et al.	2008-12-11
Agitation Of Electrolytic Solution In Electrodeposition App 20080271995 - Savastiouk; Sergey ; et al.	2008-11-06
Integrated Circuits With Conductive Features In Through Holes Passing Through Other Conductive Features And Through A Semiconductor Substrate App 20080164574 - Savastiouk; Sergey ; et al.	2008-07-10
Integrated Circuits With Conductive Features In Through Holes Passing Through Other Conductive Features And Through A Semiconductor Substrate App 20080136038 - Savastiouk; Sergey ; et al.	2008-06-12
Dielectric Trenches, Nickel/tantalum Oxide Structures, And Chemical Mechanical Polishing Techniques App 20080025009 - Savastiouk; Sergey ; et al.	2008-01-31
Dielectric trenches, nickel/tantalum oxide structures,and chemical mechanical polishing techniques App 20070257367 - Savastiouk; Sergey ; et al.	2007-11-08
Attachment of integrated circuit structures and other substrates to substrates with vias Grant 7,241,641 - Savastiouk , et al. July 10, 2	2007-07-10
Attachment of integrated circuit structures and other substrates to substrates with vias Grant 7,241,675 - Savastiouk , et al. July 10, 2	2007-07-10
Electroplating And Electroless Plating Of Conductive Materials Into Openings, And Structures Obtained Thereby App 20070128868 - Halahan; Patrick A. ; et al.	2007-06-07
Packaging substrates for integrated circuits and soldering methods Grant 7,060,601 - Savastiouk , et al. June 13, 2	2006-06-13
Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities Grant 7,049,170 - Savastiouk , et al. May 23, 2	2006-05-23
Packaging substrates for integrated circuits and soldering methods Grant 7,034,401 - Savastiouk , et al. April 25, 2	2006-04-25
Attachment of integrated circuit structures and other substrates to substrates with vias App 20060076661 - Savastiouk; Sergey ; et al.	2006-04-13
Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities App 20060035416 - Savastiouk; Sergey ; et al.	2006-02-16
Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities App 20050212127 - Savastiouk, Sergey ; et al.	2005-09-29
Packaging substrates for integrated circuits and soldering methods App 20050189636 - Savastiouk, Sergey ; et al.	2005-09-01
Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby App 20050170647 - Halahan, Patrick A. ; et al.	2005-08-04
Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities App 20050136634 - Savastiouk, Sergey ; et al.	2005-06-23
Attachment of integrated circuit structures and other substrates to substrates with vias App 20050136635 - Savastiouk, Sergey ; et al.	2005-06-23
Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby Grant 6,897,148 - Halahan , et al. May 24, 2	2005-05-24
Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby App 20040203224 - Halahan, Patrick A. ; et al.	2004-10-14
Plasma processing comprising three rotational motions of an article being processed Grant 6,749,764 - Siniaguine , et al. June 15, 2	2004-06-15
Packaging of integrated circuits and vertical integration Grant 6,693,361 - Siniaguine , et al. February 17, 2	2004-02-17
Plasma processing comprising three rotational motions of an article being processed App 20040016406 - Siniaguine, Oleg ; et al.	2004-01-29
Brim and gas escape for non-contact wafer holder Grant 6,667,242 - Siniaguine , et al. December 23, 2	2003-12-23
Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners Grant 6,498,074 - Siniaguine , et al. December 24, 2	2002-12-24
Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners Grant 6,448,153 - Siniaguine , et al. September 10, 2	2002-09-10
Non-contact workpiece holder Grant 6,402,843 - Siniaguine , et al. June 11, 2	2002-06-11
Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners App 20020013061 - Siniaguine, Oleg ; et al.	2002-01-31
Package of integrated circuits and vertical integration Grant 6,322,903 - Siniaguine , et al. November 27, 2	2001-11-27
Birm and gas escape for non-contact wafer holder App 20010002613 - Siniaguine, Oleg ; et al.	2001-06-07
Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners App 20010001215 - Siniaguine, Oleg ; et al.	2001-05-17

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