Sautter; Rolf

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sautter; Rolf.The latest application filed is for "integrated circuit including logic circuitry".

Company Profile

8.45.43

Sautter; Rolf - Bondorf DE
Sautter; Rolf - Pondorf DE
Sautter; Rolf - Boeblingen DE
Sautter; Rolf - Boudorf DE
Sautter; Rolf - Hondorf DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit including logic circuitry Grant 11,328,110 - Pille , et al. May 10, 2	2022-05-10
Integrated circuit with vertical structures on nodes of a grid Grant 11,171,142 - Pille , et al. November 9, 2	2021-11-09
Microelectronic device with a memory element utilizing stacked vertical devices Grant 11,164,879 - Pille , et al. November 2, 2	2021-11-02
Integrated Circuit Including Logic Circuitry App 20210312116 - Pille; Juergen ; et al.	2021-10-07
Buried conductive layer supplying digital circuits Grant 10,833,089 - Pille , et al. November 10, 2	2020-11-10
Layout of a memory cell of an integrated circuit Grant 10,831,970 - Sautter , et al. November 10, 2	2020-11-10
Microelectronic device utilizing stacked vertical devices Grant 10,804,266 - Pille , et al. October 13, 2	2020-10-13
Layout Of A Memory Cell Of An Integrated Circuit App 20200320174 - Sautter; Rolf ; et al.	2020-10-08
Microelectronic Device Utilizing Stacked Vertical Devices App 20200161300 - PILLE; Juergen ; et al.	2020-05-21
Buried Conductive Layer Supplying Digital Circuits App 20200161312 - PILLE; Juergen ; et al.	2020-05-21
Microelectronic Device With A Memory Element Utilizing Stacked Vertical Devices App 20200161311 - PILLE; Juergen ; et al.	2020-05-21
Integrated Circuit With Vertical Structures On Nodes Of A Grid App 20200161310 - PILLE; Juergen ; et al.	2020-05-21
Testing content addressable memory and random access memory Grant 10,593,420 - Barowski , et al.	2020-03-17
Content addressable memory cell and array Grant 10,553,282 - Darla , et al. Fe	2020-02-04
Testing content addressable memory and random access memory Grant 10,170,199 - Barowski , et al. J	2019-01-01
Testing content addressable memory and random access memory Grant 10,079,070 - Barowski , et al. September 18, 2	2018-09-18
Testing Content Addressable Memory And Random Access Memory App 20180174666 - Barowski; Harry ; et al.	2018-06-21
Structure for reducing pre-charge voltage for static random-access memory arrays Grant 10,002,661 - Fritsch , et al. June 19, 2	2018-06-19
Testing Content Addressable Memory And Random Access Memory App 20180151248 - Barowski; Harry ; et al.	2018-05-31
Testing Content Addressable Memory And Random Access Memory App 20180114585 - Barowski; Harry ; et al.	2018-04-26
Current-mode sense amplifier and reference current circuitry Grant 9,767,872 - Fritsch , et al. September 19, 2	2017-09-19
Design Structure For Reducing Pre-charge Voltage For Static Random-access Memory Arrays App 20170243633 - Fritsch; Alexander ; et al.	2017-08-24
Structure for reducing pre-charge voltage for static random-access memory arrays Grant 9,727,680 - Fritsch , et al. August 8, 2	2017-08-08
Structure for reducing pre-charge voltage for static random-access memory arrays Grant 9,721,050 - Fritsch , et al. August 1, 2	2017-08-01
Structure for reducing pre-charge voltage for static random-access memory arrays Grant 9,721,049 - Fritsch , et al. August 1, 2	2017-08-01
Content addressable memory array comprising geometric footprint and RAM cell block located between two parts of a CAM cell block Grant 9,666,278 - Fritsch , et al. May 30, 2	2017-05-30
Design Structure For Reducing Pre-charge Voltage For Static Random-access Memory Arrays App 20170047112 - Fritsch; Alexander ; et al.	2017-02-16
Design Structure For Reducing Pre-charge Voltage For Static Random-access Memory Arrays App 20170046465 - Fritsch; Alexander ; et al.	2017-02-16
Design Structure For Reducing Pre-charge Voltage For Static Random-access Memory Arrays App 20170047111 - Fritsch; Alexander ; et al.	2017-02-16
Current-mode sense amplifier and reference current circuitry Grant 9,564,188 - Fritsch , et al. February 7, 2	2017-02-07
Transforming a phase-locked-loop generated chip clock signal to a local clock signal Grant 9,537,474 - Chan , et al. January 3, 2	2017-01-03
Content addressable memory device Grant 9,536,608 - Fritsch , et al. January 3, 2	2017-01-03
Transforming A Phase-locked-loop Generated Chip Clock Signal To A Local Clock Signal App 20160344377 - CHAN; Yuen Hung ; et al.	2016-11-24
Current-Mode Sense Amplifier and Reference Current Circuitry App 20160336049 - Fritsch; Alexander ; et al.	2016-11-17
Current-mode sense amplifier Grant 9,484,073 - Fritsch , et al. November 1, 2	2016-11-01
Structure for reducing pre-charge voltage for static random-access memory arrays Grant 9,431,098 - Fritsch , et al. August 30, 2	2016-08-30
Hierarchical negative bitline boost write assist for SRAM memory devices Grant 9,431,096 - Fritsch , et al. August 30, 2	2016-08-30
Transforming a phase-locked-loop generated chip clock signal to a local clock signal Grant 9,401,698 - Chan , et al. July 26, 2	2016-07-26
Content Addressable Memory Array App 20160099053 - Fritsch; Alexander ; et al.	2016-04-07
Current-Mode Sense Amplifier and Reference Current Circuitry App 20160071555 - Fritsch; Alexander ; et al.	2016-03-10
Content Addressable Memory Cell And Array App 20160049198 - Darla; Ananth Nag Raja ; et al.	2016-02-18
Advanced array local clock buffer base block circuit Grant 9,098,659 - Dengler , et al. August 4, 2	2015-08-04
Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages Grant 8,942,052 - Huott , et al. January 27, 2	2015-01-27
Complementary Metal-Oxide-Semiconductor (CMOS) Min/Max Voltage Circuit for Switching Between Multiple Voltages App 20140140157 - Huott; William V. ; et al.	2014-05-22
Advanced Array Local Clock Buffer Base Block Circuit App 20140137070 - Dengler; Osama ; et al.	2014-05-15
Enhanced power savings for memory arrays Grant 8,659,963 - Dengler , et al. February 25, 2	2014-02-25
Enhanced Power Savings for Memory Arrays App 20130176795 - Dengler; Osama ; et al.	2013-07-11
Reduced Leakage Banked Wordline Header App 20130128684 - Buettner; Stefan ; et al.	2013-05-23
Reduced power consumption memory circuitry Grant 8,422,313 - Buettner , et al. April 16, 2	2013-04-16
Advanced Array Local Clock Buffer Base Block Circuit App 20130091375 - Dengler; Osama ; et al.	2013-04-11
Low power programmable clock delay generator with integrated decode function Grant 8,237,481 - Chan , et al. August 7, 2	2012-08-07
Reduced Power Consumption Memory Circuitry App 20120155188 - Buettner; Stefan ; et al.	2012-06-21
Adder structure with midcycle latch for power reduction Grant 8,086,657 - Haller , et al. December 27, 2	2011-12-27
Enhanced programmable pulsewidth modulating circuit for array clock generation Grant 7,936,638 - Chan , et al. May 3, 2	2011-05-03
Progamable control clock circuit for arrays Grant 7,936,198 - Sautter , et al. May 3, 2	2011-05-03
Enhanced Programmable Pulsewidth Modulating Circuit For Array Clock Generation App 20100302895 - Chan; Yuen H. ; et al.	2010-12-02
Single-ended read and differential write scheme Grant 7,813,163 - Pille , et al. October 12, 2	2010-10-12
Circuit combining level shift function with gated reset Grant 7,755,394 - Froehnel , et al. July 13, 2	2010-07-13
Progamable Control Clock Circuit For Arrays App 20100164586 - Sautter; Rolf ; et al.	2010-07-01
Array delete mechanisms for shipping a microprocessor with defective arrays Grant 7,650,535 - Hagspiel , et al. January 19, 2	2010-01-19
Low Power Programmable Clock Delay Generator with Integrated Decode Function App 20090267667 - Chan; Yuen H. ; et al.	2009-10-29
Circuit Combining Level Shift Function with Gated Reset App 20090058465 - Froehnel; Thomas ; et al.	2009-03-05
Single-ended read and differential write scheme App 20090059688 - Pille; Juergen ; et al.	2009-03-05
Method And Structure For Domino Read Bit Line And Set Reset Latch App 20080298137 - Chan; Yuen Hung ; et al.	2008-12-04
Novel Adder Structure with Midcycle Latch for Power Reduction App 20080294706 - Haller; Wilhelm ; et al.	2008-11-27
Tri-State Circuit Element Plus Tri-State-Multiplexer Circuitry App 20080258769 - Franger; Dirk ; et al.	2008-10-23
Adder structure with midcycle latch for power reduction Grant 7,406,495 - Haller , et al. July 29, 2	2008-07-29
Power saving by disabling cyclic bitline precharge Grant 7,295,481 - Pille , et al. November 13, 2	2007-11-13
Midcycle latch for power saving and switching reduction Grant 7,224,190 - Haller , et al. May 29, 2	2007-05-29
Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates Grant 7,095,252 - Haase , et al. August 22, 2	2006-08-22
Clock driver and boundary latch for a multi-port SRAM Grant 6,990,038 - Chan , et al. January 24, 2	2006-01-24
Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environments Grant 6,918,119 - Haller , et al. July 12, 2	2005-07-12
Midcycle latch for power saving and switching reduction App 20050134316 - Haller, Wilhelm ; et al.	2005-06-23
Novel adder structure with midcycle latch for power reduction App 20050138103 - Haller, Wilhelm ; et al.	2005-06-23
Power Saving By Disabling Cyclic Bitline Precharge App 20050117421 - Pille, Juergen ; et al.	2005-06-02
Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates App 20050040861 - Haase, Michael ; et al.	2005-02-24
Read/write alignment scheme for port reduction of multi-port SRAM cells Grant 6,785,781 - Leenstra , et al. August 31, 2	2004-08-31
Method and system for fast access to a translation lookaside buffer Grant 6,681,313 - Trong , et al. January 20, 2	2004-01-20
Multiple port memory apparatus Grant 6,629,215 - Pille , et al. September 30, 2	2003-09-30
Content addressable memory App 20020075713 - Hellner, Gerhard ; et al.	2002-06-20
Active window management for reorder buffer App 20010052055 - Haller, Wilhelm E. ; et al.	2001-12-13
Multiple port memory apparatus App 20010044882 - Pille, Juergen ; et al.	2001-11-22
Read/write alignment scheme for port red uction of multi-port SRAM cells App 20010034817 - Leenstra, Jens ; et al.	2001-10-25