Saulsbury; Ashley

Patent Applications and Registrations

Patent applications and USPTO patent grants for Saulsbury; Ashley.The latest application filed is for "methods and apparatus for dynamic mapping of power outlets".

Company Profile

1.27.17

Saulsbury; Ashley - Los Gatos CA
Saulsbury; Ashley - Los Altos CA
Saulsbury; Ashley - Menlo Park CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Hierarchical resource groups for providing segregated management access to a distributed switch Grant 10,868,716 - Cook , et al. December 15, 2	2020-12-15
Systems, methods, and devices for producing evancescent audio waves Grant 10,764,707 - Porter , et al. Sep	2020-09-01
Hierarchical resource groups for providing segregated management access to a distributed switch Grant 9,954,732 - Cook , et al. April 24, 2	2018-04-24
Methods And Apparatus For Dynamic Mapping Of Power Outlets App 20150301571 - SAULSBURY; Ashley ; et al.	2015-10-22
Hierarchical resource groups for providing segregated management access to a distributed switch Grant 9,106,527 - Cook , et al. August 11, 2	2015-08-11
Methods and apparatus for dynamic mapping of power outlets Grant 8,937,885 - Saulsbury , et al. January 20, 2	2015-01-20
Method and message handling hardware structure for virtualization and isolation of partitions Grant 8,707,332 - Saulsbury , et al. April 22, 2	2014-04-22
Method And Message Handling Hardware Structure For Virtualization And Isolation Of Partitions App 20120317588 - Saulsbury; Ashley ; et al.	2012-12-13
Method and message handling hardware structure for virtualization and isolation of partitions Grant 8,266,633 - Saulsbury , et al. September 11, 2	2012-09-11
Methods And Apparatus For Dynamic Mapping Of Power Outlets App 20120155328 - SAULSBURY; Ashley ; et al.	2012-06-21
Methods and apparatus for performing pixel average operations Grant 7,558,816 - Saulsbury , et al. July 7, 2	2009-07-07
Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes Grant 7,543,132 - Grohoski , et al. June 2, 2	2009-06-02
Snooping countermeasures for system indicators Grant 7,489,878 - Saulsbury February 10, 2	2009-02-10
Level 2 cache index hashing to avoid hot spots Grant 7,290,116 - Grohoski , et al. October 30, 2	2007-10-30
Logging of level-two cache transactions into banks of the level-two cache for system rollback Grant 7,191,292 - Chaudhry , et al. March 13, 2	2007-03-13
Processing architecture having parallel arithmetic capability Grant 7,124,160 - Saulsbury , et al. October 17, 2	2006-10-17
VLIW computer processing architecture having the problem counter stored in a register file register Grant 7,080,234 - Saulsbury , et al. July 18, 2	2006-07-18
Logging of level-two cache transactions into banks of the level-two cache for system rollback App 20060136672 - Chaudhry; Shailender ; et al.	2006-06-22
Processing architecture having a compare capability Grant 7,028,170 - Saulsbury April 11, 2	2006-04-11
Computer processing architecture having a scalable number of processing paths and pipelines Grant 7,020,763 - Saulsbury , et al. March 28, 2	2006-03-28
Methods and apparatus for performing parallel integer multiply accumulate operations Grant 7,013,321 - Saulsbury March 14, 2	2006-03-14
VLIW computer processing architecture having a scalable number of register files Grant 6,988,181 - Saulsbury , et al. January 17, 2	2006-01-17
Processing architecture having an array bounds check capability Grant 6,892,295 - Saulsbury May 10, 2	2005-05-10
Snooping countermeasures for system indicators App 20050035202 - Saulsbury, Ashley	2005-02-17
Processing architecture having field swapping capability Grant 6,816,961 - Rice , et al. November 9, 2	2004-11-09
VLIW computer processing architecture with on-chip dynamic RAM Grant 6,631,439 - Saulsbury , et al. October 7, 2	2003-10-07
Methods and apparatus for performing parallel integer multiply accumulate operations App 20030097391 - Saulsbury, Ashley	2003-05-22
Methods and apparatus for performing pixel average operations App 20030097389 - Saulsbury, Ashley ; et al.	2003-05-22
VLIW computer processing architecture with on-chip DRAM usable as physical memory or cache memory App 20020087821 - Saulsbury, Ashley ; et al.	2002-07-04
Computer processing architecture having a scalable number of processing paths and pipelines App 20020049892 - Saulsbury, Ashley ; et al.	2002-04-25
Processing architecture having field swapping capability App 20020035678 - Rice, Daniel S. ; et al.	2002-03-21
Processing architecture having parallel arithmetic capability App 20020035589 - Saulsbury, Ashley ; et al.	2002-03-21
VLIW computer processing architecture with on-chip dynamic RAM App 20020032831 - Saulsbury, Ashley ; et al.	2002-03-14
Processing architecture having a matrix-transpose capability App 20020032710 - Saulsbury, Ashley ; et al.	2002-03-14
VLIW computer processing architecture having the program counter stored in a register file register App 20020032849 - Saulsbury, Ashley ; et al.	2002-03-14
Processing architecture having an array bounds check capability App 20020029332 - Saulsbury, Ashley	2002-03-07
VLIW computer processing architecture having a scalable number of register files App 20020023201 - Saulsbury, Ashley ; et al.	2002-02-21
Processing architecture having a compare capability App 20020019928 - Saulsbury, Ashley	2002-02-14
Microprocessor with reduced context switching overhead and corresponding method Grant 6,314,510 - Saulsbury , et al. November 6, 2	2001-11-06
Processor/memory device with integrated CPU, main memory, and full width cache and associated method Grant 6,199,142 - Saulsbury , et al. March 6, 2	2001-03-06
Integrated processor/memory device with victim data cache Grant 5,900,011 - Saulsbury , et al. May 4, 1	1999-05-04

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