loadpatents
name:-0.011508941650391
name:-0.018337965011597
name:-0.0085358619689941
Saulnier; Nicole A. Patent Filings

Saulnier; Nicole A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Saulnier; Nicole A..The latest application filed is for "self aligned pattern formation post spacer etchback in tight pitch configurations".

Company Profile
9.29.22
  • Saulnier; Nicole A. - Albany NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Self Aligned Pattern Formation Post Spacer Etchback In Tight Pitch Configurations
App 20210280422 - Burns; Sean D. ;   et al.
2021-09-09
Structure and method for equal substrate to channel height between N and P fin-FETs
Grant 11,043,494 - Clevenger , et al. June 22, 2
2021-06-22
FinFET gate cut after dummy gate removal
Grant 11,024,715 - Sporre , et al. June 1, 2
2021-06-01
Photoresist bridging defect removal by reverse tone weak developer
Grant 11,022,891 - Bi , et al. June 1, 2
2021-06-01
Photoresist bridging defect removal by reverse tone weak developer
Grant 11,022,890 - Bi , et al. June 1, 2
2021-06-01
Self aligned pattern formation post spacer etchback in tight pitch configurations
Grant 11,018,007 - Burns , et al. May 25, 2
2021-05-25
Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs
Grant 10,957,583 - Burns , et al. March 23, 2
2021-03-23
Finfet Gate Cut After Dummy Gate Removal
App 20200243648 - Sporre; John R. ;   et al.
2020-07-30
FinFET gate cut after dummy gate removal
Grant 10,600,868 - Sporre , et al.
2020-03-24
Self Aligned Pattern Formation Post Spacer Etchback In Tight Pitch Configurations
App 20200075336 - Burns; Sean D. ;   et al.
2020-03-05
Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs
Grant 10,546,774 - Burns , et al. Ja
2020-01-28
Self aligned pattern formation post spacer etchback in tight pitch configurations
Grant 10,529,569 - Burns , et al. J
2020-01-07
Self-aligned Quadruple Patterning (saqp) For Routing Layouts Including Multi-track Jogs
App 20190393082 - Burns; Sean D. ;   et al.
2019-12-26
Enhanced self-alignment of vias for a semiconductor device
Grant 10,515,894 - Briggs , et al. Dec
2019-12-24
Structure And Method For Equal Substrate To Channel Height Between N And P Fin-fets
App 20190326289 - CLEVENGER; Lawrence A. ;   et al.
2019-10-24
Self aligned conductive lines with relaxed overlay
Grant 10,395,985 - Burns , et al. A
2019-08-27
Structure and method for equal substrate to channel height between N and P fin-FETs
Grant 10,381,348 - Clevenger , et al. A
2019-08-13
Vertical transport FET with two or more gate lengths
Grant 10,361,127 - Karve , et al.
2019-07-23
Vertical Transport Fet With Two Or More Gate Lengths
App 20190206738 - Karve; Gauri ;   et al.
2019-07-04
Finfet Gate Cut After Dummy Gate Removal
App 20190189517 - Sporre; John R. ;   et al.
2019-06-20
Method and structure for forming a replacement contact
Grant 10,249,533 - Shearer , et al.
2019-04-02
Separate N and P fin etching for reduced CMOS device leakage
Grant 10,229,910 - Chu , et al.
2019-03-12
FinFET gate cut after dummy gate removal
Grant 10,229,854 - Sporre , et al.
2019-03-12
Enhanced self-alignment of vias for asemiconductor device
Grant 10,211,151 - Briggs , et al. Feb
2019-02-19
Self Aligned Pattern Formation Post Spacer Etchback In Tight Pitch Configurations
App 20180350599 - Burns; Sean D. ;   et al.
2018-12-06
Self aligned pattern formation post spacer etchback in tight pitch configurations
Grant 10,121,661 - Burns , et al. November 6, 2
2018-11-06
Self aligned conductive lines with relaxed overlay
Grant 10,083,864 - Burns , et al. September 25, 2
2018-09-25
Enhanced Self-alignment Of Vias For A Semiconductor Device
App 20180254242 - BRIGGS; Benjamin D. ;   et al.
2018-09-06
Photoresist Bridging Defect Removal By Reverse Tone Weak Developer
App 20180239254 - Bi; Zhenxing ;   et al.
2018-08-23
Photoresist Bridging Defect Removal By Reverse Tone Weak Developer
App 20180239253 - Bi; Zhenxing ;   et al.
2018-08-23
Self Aligned Conductive Lines With Relaxed Overlay
App 20180233408 - Burns; Sean D. ;   et al.
2018-08-16
Self-aligned Quadruple Patterning (saqp) For Routing Layouts Including Multi-track Jogs
App 20180233403 - Burns; Sean D. ;   et al.
2018-08-16
Self Aligned Pattern Formation Post Spacer Etchback In Tight Pitch Configurations
App 20180197738 - Burns; Sean D. ;   et al.
2018-07-12
Structure And Method For Equal Substrate To Channel Height Between N And P Fin-fets
App 20180197858 - CLEVENGER; Lawrence A. ;   et al.
2018-07-12
Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs
Grant 9,991,156 - Burns , et al. June 5, 2
2018-06-05
Separate N And P Fin Etching For Reduced Cmos Device Leakage
App 20180097002 - Chu; Isabel C. ;   et al.
2018-04-05
Self aligned pattern formation post spacer etchback in tight pitch configurations
Grant 9,934,970 - Burns , et al. April 3, 2
2018-04-03
Self aligned conductive lines
Grant 9,911,647 - Burns , et al. March 6, 2
2018-03-06
Self Aligned Conductive Lines With Relaxed Overlay
App 20180005885 - Burns; Sean D. ;   et al.
2018-01-04
Self Aligned Conductive Lines
App 20170358487 - Burns; Sean D. ;   et al.
2017-12-14
Self-aligned Quadruple Patterning (saqp) For Routing Layouts Including Multi-track Jogs
App 20170352585 - Burns; Sean D. ;   et al.
2017-12-07
Self aligned conductive lines
Grant 9,786,554 - Burns , et al. October 10, 2
2017-10-10
Method and structure for cut material selection
Grant 9,779,944 - Burns , et al. October 3, 2
2017-10-03
Separate N and P fin etching for reduced CMOS device leakage
Grant 9,711,507 - Chu , et al. July 18, 2
2017-07-18
Interconnect structure having large self-aligned vias
Grant 9,659,820 - Zhang , et al. May 23, 2
2017-05-23
Interconnect structure having large self-aligned vias
Grant 9,658,523 - Zhang , et al. May 23, 2
2017-05-23
Self aligned conductive lines with relaxed overlay
Grant 9,607,886 - Burns , et al. March 28, 2
2017-03-28
Interconnect Structure Having Large Self-aligned Vias
App 20160247722 - Zhang; John H. ;   et al.
2016-08-25
Interconnect structure having large self-aligned vias
Grant 9,391,020 - Zhang , et al. July 12, 2
2016-07-12
Interconnect Structure Having Large Self-aligned Vias
App 20150279780 - Zhang; John H. ;   et al.
2015-10-01
Interconnect Structure Having Large Self-aligned Vias
App 20150279784 - Zhang; John H. ;   et al.
2015-10-01

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