Sarwary; Mohamed Shaker

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sarwary; Mohamed Shaker.The latest application filed is for "formal clock network analysis, visualization, verification and generation".

Company Profile

3.14.15

Sarwary; Mohamed Shaker - San Diego CA
Sarwary; Mohamed Shaker - Union City CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Formal clock network analysis, visualization, verification and generation Grant 10,599,800 - Sarwary , et al.	2020-03-24
System and method for managing and composing verification engines Grant 10,387,605 - Mneimneh , et al. A	2019-08-20
Reset domain crossing management using unified power format Grant 10,289,773 - Shah , et al.	2019-05-14
Formal Clock Network Analysis, Visualization, Verification and Generation App 20190034571 - Sarwary; Mohamed Shaker ; et al.	2019-01-31
Reset Domain Crossing Management Using Unified Power Format App 20180004876 - Shah; Deep ; et al.	2018-01-04
System and method for netlist clock domain crossing verification Grant 9,721,057 - Ganai , et al. August 1, 2	2017-08-01
System and method for reactive initialization based formal verification of electronic logic design Grant 9,721,058 - Sarwary , et al. August 1, 2	2017-08-01
System And Method For Managing And Composing Verification Engines App 20170024508 - Mneimneh; Maher ; et al.	2017-01-26
Method And System For Checking And Correcting Shoot-through In Rtl Simulation App 20160342727 - Sarwary; Mohamed Shaker ; et al.	2016-11-24
System And Method For Reactive Initialization Based Formal Verification Of Electronic Logic Design App 20160300009 - Sarwary; Mohamed Shaker ; et al.	2016-10-13
System And Method For Netlist Clock Domain Crossing Verification App 20160259879 - Ganai; Malay ; et al.	2016-09-08
Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design Grant 9,208,272 - Sarwary December 8, 2	2015-12-08
System And Method For Abstraction Of A Circuit Portion Of An Integrated Circuit App 20150234973 - Sarwary; Mohamed Shaker ; et al.	2015-08-20
System and method for a hybrid clock domain crossing verification Grant 8,984,457 - Sarwary , et al. March 17, 2	2015-03-17
System And Method For A Hybrid Clock Domain Crossing Verification App 20140282321 - Sarwary; Mohamed Shaker ; et al.	2014-09-18
System And Method For Filtration Of Error Reports Respective Of Static And Quasi-static Signals Within An Integrated Circuit Design App 20140282322 - Sarwary; Mohamed Shaker ; et al.	2014-09-18
System and method for abstraction of a circuit portion of an integrated circuit Grant 8,656,328 - Sarwary , et al. February 18, 2	2014-02-18
Apparatus And Method Thereof For Hybrid Timing Exception Verification Of An Integrated Circuit Design App 20140040841 - SARWARY; Mohamed Shaker	2014-02-06
Hierarchical bottom-up clock domain crossing verification Grant 8,607,173 - Sarwary , et al. December 10, 2	2013-12-10
Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design Grant 8,560,988 - Sarwary October 15, 2	2013-10-15
Hierarchical Bottom-up Clock Domain Crossing Verification App 20130239080 - SARWARY; Mohamed Shaker ; et al.	2013-09-12
Apparatus And Method Thereof For Hybrid Timing Exception Verification Of An Integrated Circuit Design App 20120042294 - SARWARY; Mohamed Shaker	2012-02-16
Method for clock synchronization validation in integrated circuit design Grant 7,506,292 - Sarwary , et al. March 17, 2	2009-03-17
Method For Clock Synchronization Validation In Integrated Circuit Design App 20060150043 - SARWARY; Mohamed Shaker ; et al.	2006-07-06
Method for clock synchronization validation in integrated circuit design Grant 7,073,146 - Sarwary , et al. July 4, 2	2006-07-04
Method for clock synchronization validation in integrated circuit design App 20050097484 - Sarwary, Mohamed Shaker ; et al.	2005-05-05

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